本論文主要致力於高線性度與面積小之「互補式二分法延遲線」之研究發展，寄望在低成本與穩定的優勢下，大幅提高其實用性。
因為容易設計及穩定的特性，延遲鎖定迴路(Delay-Locked Loop)已經比鎖相迴路(Phase-Locked Loop)更廣泛地應用在時脈誤差調整上。不僅如此，在現今有越來越多的應用開始使用延遲鎖定迴路，例如隨機存取記憶體與時脈產生器，而這一些應用在以前只能使用鎖相迴路。因此，在不久的未來，延遲鎖定迴路將會更加重要，所以本論文新穎的架構是將延遲鎖定迴路 (DLL) 的技術配合在數位脈波寬度調變電路（DPWM）上。
在本論文中主要針對數位脈波寬度調變和延遲鎖定迴路作說明以及討論，並且使用TSMC 0.35μm 2P4M CMOS 製程，供應電壓為3.3V；所提及數位脈波寬度調變電路操作在400KHz頻率下，解析度為9.8ns且一次線性誤差約小於0.3%。此晶片面積只有0.9*0.41 mm2。

This research focuses on the design of key component,“Complementary Half Delay-Line(CHDL). ”It will significantly improve the practicability under the superiority of extremely low cost and stable.
Delay-Locked Loops (DLLs) have been widely used for clock deskew in stead of Phase-Locked Loop (PLLs) because of easy design and inherent stable. In nowadays, more and more applications, such as dram and clock generator where only used with PLLs in the past and are employed DLLs. So, the DLLs will be more significant in the near future. This research proposes a new structure is DLLs use in DPWM.
The main object of this research is the description and discussion in DPWM and DLLs, uses TSMC 0.35μm 2P4M CMOS process to design a DPWM and the supply voltage is 3.3V. The proposed DPWM resolution is 9.8ns and the similar first order curvature correction error is less than 0.3% in 400 KHz operation frequency. The chip area is merely 0.9*0.41 μm mm2

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