由於各家處理器的指令集架構(ISA，instruction set architecture)不相同，同一程式無法在不同處理器上執行，因此必須透過Binary Translation技術，將一平台的執行程式先轉換到可重標地編譯器(Retargetable Compilers)的IR(Intermediate Representation)，再由編譯器將IR編譯成另一指令集的執行檔。
Binary Translation如果只是單純的將暫存器名稱當作變數名稱，將程式傳換到IR，彼此變數的定義和使用的相依關係在轉譯的過程中依然存在著，這樣的關係影響到暫存器的重新分配，導致新的平台即使擁有更多的暫存器可以使用，還是無法辨識出和消除原有的Register Spills並將值存放到可利用的暫存器，以達到減少Register Spills次數的目的。
在這篇論文中，我們提出Register Virtualization的觀念，Register Virtualization的目的是消除因為暫存器不足而產生的Register Spills，將原本的實體暫存器轉換成虛擬暫存器。編譯器後端的Register Allocator就可將虛擬暫存器分配到新平台上的實體暫存器，以增進暫存器的使用效率，達到提升程式執行效率的目的。

As the same binary programs can not be executed directly on processors with different ISAs (Instruction Set Architectures), binary translation is applied to translating the binary programs from one ISA to another. Nowadays indirect binary translation is the most common-used approach, which converts the source binary programs into the intermediate representation (IR) of a retargetable compiler and then uses the backend of the compiler to translate IR to the target programs.
During the process of building IR of the source programs, the registers of the source programs can be treated as normal variables and then be translated to IR. The relationship between registers still exists, this relationship affect register reallocation. If the target programs have more registers can be use, we can not examine load/store instructions to identify register spills and reduce the number of register spills
In this paper, we propose the concept of the register virtualization, the purpose of register virtualization is analyze the def-use relations of accesses of physical registers and examine load/store instructions to identify register spills, and then translate them to virtual registers. The backend of the retargetable compiler then can allocate these virtual registers onto the physical registers of the target platform. We implement register virtualization with Floating Accumulator architecture. This can facilitate the compiler utilizing the extra registers to reduce register spills.

[1] ARM Limited. ARM9TDMITM Technical Reference Manual,2000.

[2] C. Lattner and V. Adve, “LLVM: A Compilation Framework for
Lifelong Program Analysis & Transformation,” in Proceedings of
the international symposium on Code generation and optimization:
feedback-directed and runtime optimization, ser. CGO ’04.
Washington, DC,USA: IEEE Computer Society, 2004, pp. 75.

[3] Todd Austin, Eric Larson, and Dan Ernst. SimpleScalar:
An infrastructure for computer system modeling.
IEEEComputer, 35(2):59–67, 2002.

[4] GCC. The GNU compiler collection. http://gcc.gnu.org/.

[5] Edil S. T. Fernandes, Anna Dolejsi Santos, and Claudio L. de Amorim. Conditional execution:
An approach for eliminatingthe basic block barriers. Microprocessing and Microprogrammin,40:689–692, 1994.

[6] Chunho Lee, Miodrag Potkonjak and William H.Mangione-Smith
MediaBeinch: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems.
In Proceeding of MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture Pages 330-335

[7] C. Lattner and V. Adve. LLVM Language Reference Manual. http://llvm.cs.uiuc.edu/docs/LangRef.html.

[8] “CLANG,” http://clang.llvm.org.

[9] G. J. Chaitin, et. al., Register allocation via coloring, In Computer Languages, Vol. 6, pages 47-57, Jan. 1981

[10] P. Briggs, K. D. Cooper, and L. Torczon, Improvements to graph
Coloring register allocation, In ACM Transactions on
Programming Languages and Systems, Vol. 16, No. 3, pages 428-455, May 1994.

[11] Sebastian Hack, Daniel Grund, and Gerhard Goos. Register allocation for programs in SSA-form. In CC '06 Proceedings of the 15th international conference on Compiler Construction, pages 247–262. Springer, 2006.

[12] F. Chow and J. Hennessy. The Priority-based Coloring Approach
to Register Allocation, In ACM Transactions on Programming Languages and Systems, Vol. 12, No. 4, 1990, pages 501-536

[13] Wei-Che Hsu and Yuan-Shin Hwang,Floating Accumulator Architecture, Advanced Science and Technology Letters, Vol. 123(CST 2016), pages 157-162

[14] David Seal, editor. ARM Architecture Reference Manual.
Addison-Wesley Professional, 2nd edition, 2001.

[15] Xiaotong Zhuang and Santosh Pande. Differential register allocation. In Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
(PLDI’05), pages 168–179, 2005.

[16] Christopher Lupo, Kent D. Wilken. Post Register Allocation Spill
Code Optimization. In: Proceedings of the international symposium on code generation and optimization, CGO ’06. IEEE, New York, page 245–255, 2006

[17] Scott Ananian. The static single information form. Master’s thesis,
MIT, September 1999.

[18] David Ryan Koes , Seth Copen Goldstein, Register allocation
deconstructed, Proceedings of th 12th International Workshop on Software and Compilers for Embedded Systems, April 23-24, 2009, Nice, France

[19] C. Cifuentes and V. M. Malhotra, “Binary Translation: Static, Dynamic,Retargetable?” in Proceedings of the 1996 International Conference on Software Maintenance, ser. ICSM ’96. Washington, DC, USA: IEEE Computer Society, 1996.

[20] C. Cifuentes and M. V. Emmerik, “UQBT: Adaptable Binary Translation at Low Cost,” Computer, vol. 33, pp. 60–66, March 2000.

[21] V. Adve, C. Lattner, M. Brukman, A. Shukla, and B. Gaeke. LLVA： A Low-level Virtual Instruction Set Architecture. In 36th Int’l Symp. on Microarchitecture, pages 205–216, San Diego, CA, Dec 2003.

[22] Life of an instruction in LLVM

[23]Getting Started with LLVM Core Libraries

[24]LLVM Cookbook

[25]LLVM Essentials