用來量測時間間隔的時間至數位轉換器(TDC)已廣泛地應用於各種用途的科學、工業、及可攜式電子裝置。為縮短數位系統的研發週期，TDC應具有全數位化、彈性、與可攜式的特性，以及針對不同的製程具擴展性。為達到此目標，本論文提出一個全數位循環式的TDC，並利用Verilog HDL (hardware description language)描述為一個可合成的智產區塊(IP block)。
本論文所提出的可合成的、擴展性的循環式TDC架構，乃利用循環式延遲時脈技術簡化控制電路以及傳統TDC架構的補償設計減低連續校正的需要，其中具擴展性循環式延遲線的級數取決於其最終的應用。有別於傳統的TDC，本論文所提出的TDC架構除了可減少連續校正的需要，針對不同的製程亦能輕易地達到彈性、擴展性、簡化、線性和可攜性。此外，提出的TDC架構在理論上還能達到無量測範圍限制以及有效率地使用電路面積。

TDCs have been widely used to measure time intervals in various scientific, industrial, and portable electronics applications. To shorten the developing cycle of such digital systems, TDCs should be all-digital, flexible, and portable, and can be scalable to different processes. To achieve this, an all-digital cyclic time-to-digital converter (TDC) is proposed and described in synthesizable Verilog HDL code so that it can be built as an IP block.
The proposed TDC uses a cyclic-delaying clock technique, where the number of stages in the cyclic delay chain is scalable and can be determined by the ultimate applications, to simplify the control circuit and the compensation scheme of traditional TDC architectures to alleviate the need of continuous calibration. Unlike the traditional TDCs, the proposed TDC architecture can alleviate the need of continuous calibration and easily achieve the flexibility, scalability, simplicity, linearity, and portability to different process technologies. Besides, it may achieve the theoretically unlimited dynamic range as well as efficient area usage.
In addition, the proposed TDC architecture is more flexible and easily adapted to many other demanding applications.

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