摘要
隨著速度的上升與功能的彈性，記憶體的時脈也越來越高，而且與(System-on-Chip，SoC)結合成為一種趨勢，因此SDRAM控制器也納入SoC內作為一個重要的模組，以有效率的驅動記憶體，達到更高的速率。
由於SoC晶片大部分皆使用ARM Cortex系列的微控制器，所以本論文選擇使用AMBA系列中的AXI4介面與SDRAM DDR4連接，並設計與實現需要的SDRAM控制器。
本論文中的SDRAM控制器分為四個區塊，分別為非同步接收AXI指令區塊、指令排程區塊、記憶體物理層、記憶體資料回傳區塊，利用AXI的隨意傳輸與burst type傳輸型態，並結合DDR4的bank group與讀寫排程，縮減WTR_time、RTW_time的執行次數，以達到加快整體效能的目的。
完成的記憶體控制器符合DDR4 SDRAM與AMBA系列AXI4規範，可以依照輸入的讀寫指令做出良好的排程，並在Xilinx ISE Spartan6 XC6SLX150上進行模擬，使用了421個邏輯閘、729個暫存器、265 LUT做為記憶體使用，操作頻率最高可達229.28MHz。

Abstract

The increasing demand for speed and flexibility of functions, the clock frequency of memory is getting higher and higher. In addition, due to the trend of integrating various modules into an SoC (System-on-Chip), embedding an SDRAM controller is of importance an efficient way to drive the memory so as to achieve high performance. Since most SoC chips use the ARM Cortex microcontrollers, in this thesis we design and implement an SDRAM controller, which connects AMBA AXI4 and DDR4 SDRAM.
The SDRAM controller is divided into four modules, including asynchronous FIFO receiving AXI instruction blocks module, the instruction scheduling module, the　memory physical layer module, and memory data return block module. We use out-of-order transmission and burst type transfer of AXI4. By combining DDR4 bank groups with the read and write scheduling, WTR_time and RTW_time execution times are reduced and overall performance is promoted.
The completed memory controller conforms to the standards of DDR4 and AMBA AXI4. The input read and write instructions are well scheduled. On the Xilinx ISE Spartan6 XC6SLX150 device, it uses 421 logic gates, 729 registers, and 265 LUTs as memory. The final operating frequency is up to 229.28 MHz.

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