本論文提出一個改良式蛇形延遲線來消除傳統蛇形延遲線所產生的遠端串音。
在第二章，我們藉由等效電路探討傳統蛇形延遲線的效能。首先，我們在頻域萃取與驗證這個等效電路。接著我們使用這個等效電路來模擬時域反射、時域穿透、近端串音與遠端串音的響應。為了要驗證這些模擬結果，我們使用TEK/CSA8200示波器與80E04時域反射模組來進行量測，量測結果驗證了模擬結果的正確性。
在第三章，我們提出一個改良式蛇形延遲線來改善傳統蛇形延遲線的效能。我們萃取這個改良式蛇形延遲線的等效電路，並且將這等效電路用在模擬時域反射、時域穿透、近端串音與遠端串音的響應。除此之外，我們也做實驗驗證這些模擬的結果。
在第四章，我們比較改良式蛇形延遲線與傳統蛇形延遲線的時域反射、時域穿透、近端串音與遠端串音的響應。由實驗的結果我們可知改良式蛇形延遲線比傳統蛇形延遲線有比較好的時域反射響應，並且在不增加近端串音的情況下，可以消除58 %或54.64 %的遠端串音。除此之外，這個改良式蛇線延遲線在限定的面積下可以增加14 %的時間延遲。
最後，在第五章我們將做一些總結。

In this thesis, an improved serpentine delay line is proposed in order to eliminate the far-end crosstalk encountered in the traditional serpentine delay line.
In Chapter 2, we investigate the performances of the traditional serpentine delay line through its equivalent circuit. Parameters of the equivalent circuit is extracted and verified in the frequency domain. This equivalent circuit is then used in simulating the responses of the time domain reflection, time domain transmission, near-end crosstalk, far-end crosstalk. Furthermore, in order to verify these simulation results, time-domain measurements are performed by using the oscilloscope TEK/CSA8200 along with the TDR module 80E04. The measurement results are in good agreements with the simulation results.
In Chapter 3, we propose an improved serpentine delay line in order to improve the performances of the traditional serpentine delay line. Parameters of the equivalent circuit are extracted and then used in the simulation of the time domain reflection, time domain transmission, near-end crosstalk, far-end crosstalk responses. Also, experiment is performed in order to verify these time-domain simulation results.
In Chapter 4, performances of the improved serpentine delay line and the traditional serpentine delay line are investigated through comparing the responses of the time domain reflection, time domain transmission, near-end crosstalk, far-end crosstalk and eye diagram. It has been shown that the improved serpentine delay line has a better time domain reflection response. Also, the far-end crosstalk is reduced approximately to 58 % or 54.64 % without increasing the near-end crosstalk. The delay time is increased 14 %, which provides a longer delay time in the limited area.
Finally, a couple of conclusions are drawn in Chapter 5.

[1] S. H. Hall, G. W. Hall, and J. A. McCall, High-Speed Digital System Design, New York: Wiley, 2000, pp. 45-48.
[2] http://home.educities.edu.tw/oldfriend/SIwave/antipad_slot.htm.
[3] K. Lee, H. B. Lee, H. K. Jung, J. Y. Sim, and H. J. Park, “Serpentine guard trace to reduce far-end crosstalk and even-odd mode velocity mismatch of microstrip lines by more than 40%,” Proceedings 57th Electronic Components and Technology Conference, pp. 329-332, May 29 - Jun. 1, 2007.
[4] R. B. Wu and F. L. Chao, “Laddering wave in serpentine delay line,” IEEE Transactions on Components, Packaging, and Manufacturing Technology, part B: Advanced Packaging, vol. 18, no. 4, pp. 644-650, Nov. 1995.
[5] R. B. Wu and F. L. Chao, “Flat spiral delay line design with minimum crosstalk penalty,” IEEE Transactions on Components, Packaging, and Manufacturing Technology, part B: Advanced Packaging, vol. 19, no. 2, pp. 397-406, May 1996.
[6] G. H. Shiue, C. Y. Chao, W. D. Guo, and R. B. Wu, “Improvements of transient transmission waveform and eye diagram in serpentine delay line with guard traces,” IEEE International Symposium on Electromagnetic Compatibility, pp. 1-5, Jul. 2007.
[7] D. Pavlidis and H. I. Hartnagel, “The design and performance of three-line microstrip couplers,” IEEE Transactions on. Microwave Theory and Techniques, vol. 24, no. 10, pp. 631-640, Oct. 1976.
[8] K. Lee, H. B. Lee, H. K. Jung, J. Y. Sim, and H. J. Park, “A serpentine guard trace to reduce the far-end crosstalk voltage and the crosstalk induced timing jitter of parallel microstrip lines,” IEEE Transactions on Advanced Packaging, vol. 31, no. 4, pp. 809-817, Nov. 2008.
[9] L. Zhi, W. Qiang, and S. Changsheng, “Application of guard traces with vias in the RF PCB layout,” Proc. 2002 3rd IEEE International Symposium on Electromagnetic Compatibility, pp. 771–774, May 2002.
[10] A. Suntives, A. Khajooezadeh, and R. Abhari, “Using via fences for crosstalk reduction in PCB circuits,” 2006 IEEE International Symposium on Electromagnetic Compatibility, vol 1, pp. 34-37, Aug. 2006.
[11] C. H. Chen, W. T. Huang, C. T. Chou, and C. H. Lu, “A novel design to prevent crosstalk,” IEEE TENCON 2007 – 2007 IEEE Region 10 conference, pp. 1-4 , Oct. 30 2007 - Nov. 2 2007.
[12] U. Choi, Y. J. Kim, and Y. S. Kim, “Crosstalk reduction in printed circuit boards using irregularly-spaced vias in guard trace over slotted ground plane”, European Conference on Circuit Theory and Design, pp.794-797, Aug. 2009.
[13] Y. S. Cheng, W. D. Guo, G. H.Shiue, H. H. Cheng, C. C. Wang, and R. B. Wu, “Fewest vias design for microstrip guard trace by using overlying dielectric,” IEEE 17th Topical Meeting on Electrical Performance of Electronic Packaging, pp. 321-324, San Jose, California, USA, Oct. 2008.
[14] Y. S. Cheng, W. D. Guo, C. P. Hung, R. B. Wu, and D. D. Zutter, “Enhanced microstrip guard trace for ringing noise suppression using a dielectric superstrate,” IEEE Transactions on Advanced Packaging, vol. PP, no. 99, pp. 1-1, Feb. 2010.
[15] P. Muthana and H. Kroger, “Behavior of short pulses on tightly coupled microstrip lines and reduction of crosstalk by using overlying dielectric,” IEEE Transactions on Advanced Packaging, vol. 30, no. 3, pp. 511-520, Aug. 2007.
[16] S. H. Hall, G. W. Hall, and J. A. McCall, High-Speed Digital System Design, New York: Wiley, 2000, pp. 329-331.