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研究生： 郭立宇
Li-Yu Kuo
論文名稱： CAM-based SRAM內建自我修復電路之設計與驗證
Design and Verification of CAM-based SRAM BISR Circuits
指導教授： 吳乾彌
Chen-Mie Wu
口試委員: 陳省隆
Hsing-Lung Chen
陳郁堂
Yie-Tarng Chen
陳漢宗
Hann-Tzong Chern
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2016
畢業學年度： 104
語文別： 中文
論文頁數： 98
中文關鍵詞： 內建自我修復
外文關鍵詞： CAM, BISR
相關次數： 點閱：114  下載：7 
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  •  上一筆

    • 本論文是有關CAM-based SRAM自我修復電路之設計與驗證，相關研究工作包含下列四大部分：
    第一部分為探討內建自我修復電路之結構，並在分析內建自我測試與故障植入電路後，發展出一個SRAM內建自我修復電路驗證系統。
    第二部分為設計與實現CAM-based SRAM自我修復電路驗證系統之硬體，其中包含了內建自我測試、故障植入與內建自我修復等電路，並以Altera FPGA開發板實現之。
    第三部分為驗證系統之軟/硬體整合設計與實現，其中包含撰寫NIOS II相關軟韌體程式來分析由內建自我測試電路所得到的資訊，並使用NIOS II來驗證其功能。
    第四部分是使用不同類型的故障來測試與驗證內建自我修復電路之功能。
    整體而言，本論文係以研究CAM-based SRAM自我修復電路驗證系統為目標，並使用Altera FPGA開發板實現之。最後，在SRAM上植入不同的故障進行測試，證實本論文所發展之內建自我修復電路有極佳的效能。

    This thesis is relevant to the design and verification of an FGPA-based verification system for the CAM-based SRAM BISR (Built-In Self-Repair) circuits. The research work consists of the following four parts.
    The first part of the thesis is to explore the architecture of a verification system for the BISR circuits. After analyzing the BIST (Built-In Self-Test) circuits and fault injection methods, a verification system for the CAM-based SRAM BISR circuit has been developed.
    The second part of the thesis is to design and implement the hardware for a CAM-based SRAM BISR verification system. It includes the BIST, fault injection, and BISR circuits. Finally, the hardware modules mentioned above are implemented on an Altera FPGA development board.
    The third part of the thesis focuses on the hardware/software co-design and implementantion of the verification system. The research work includes writing NIOS II-related software and firmware programs to analyze the fault information generated by the BIST hardware. Meanwhile, NIOS II is used to verify the functionality of the verification system.
    The fourth part focuses on using the different kinds of faults to test and verify the function of the BISR circuit.
    As a whole, the goal of this thesis is to do the research on a verification system for the CAM-based SRAM BISR system and implement it on an FPGA development board. Finally, by injecting SRAM with various faults for testing, the CAM-based SRAM BISR circuit developed in this thesis has been proved to have great performance.

    第一章 緒論 10 1.1 研究背景與動機 10 1.2 研究內容之相關結構 11 1.3 論文組織與概觀 12 第二章 CAM-based SRAM自我修復系統之發展環境與驗證流程 13 2.1 SOPC-based 軟/硬體整合設計簡介 13 2.2 Altera SOPC-based軟體開發環境 15 2.3 Altera SOPC-based硬體開發環境 16 2.3.1 NIOS II IDE 16 2.3.1.1 NIOS II 處理器結構 17 2.3.1.2 Avalon Bus結構 18 2.3.2 Quartus II發展系統 20 2.3.3 Altera Stratix II FPGA 開發板 22 2.4 CAM-based SRAM自我修復系統之開發驗證流程 23 2.4.1 CAM-based SRAM自我修復系統之結構介紹 23 2.4.2 CAM-based SRAM自我修復系統之軟體模擬與驗證 25 2.4.3 CAM-based SRAM自我修復系統之硬體開發與驗證 27 第三章 CAM-based SRAM自我修復系統之硬體結構與概念 29 3.1 CAM-based SRAM自我修復系統電路之硬體結構介紹 29 3.2 SRAM內建自我測試電路 31 3.2.1 SRAM故障模型介紹 31 3.2.2 March-based SRAM自我測試演算法 33 3.2.3 SRAM內建自我測試電路結構 34 3.3 SRAM故障植入電路 36 3.3.1 SRAM故障之軟體模擬 36 3.3.2 SRAM故障之硬體模擬 36 3.3.3 SRAM故障之植入 36 3.4 CAM-based內建自我修復電路 38 3.4.1 Content-Addressable Memory介紹 38 3.4.1.1 Content-Addressable Memory的結構 38 3.4.1.2 Content-Addressable Memory的優勢 39 3.4.2 CAM-based內建自我修復電路之結構 40 第四章CAM-based SRAM自我修復系統之硬體設計與實現 42 4.1 CAM-based SRAM自我修復系統之硬體結構 42 4.2 SRAM記憶體的硬體故障設計與模擬 45 4.2.1 SRAM的結構 45 4.2.2 SRAM硬體故障植入之結構 46 4.2.3 SRAM硬體故障植入之設計 49 4.3 FPGA-based內建自我測試電路之設計與實現 52 4.3.1 March記憶體測試演算法之硬體設計 52 4.3.2 FPGA-based內建自我測試電路之硬體設計 55 4.3.3 FPGA-based內建自我測試電路之資料儲存格式 60 4.4 FPGA-based內建自我修復電路之設計與實現 61 4.4.1 FPGA-based內建自我修復電路之硬體設計 62 4.4.2 FPGA-based內建自我修復電路之資料儲存格式 68 4.5 CAM-based SRAM自我修復系統之軟硬體整合設計 69 4.5.1 故障資料之分析演算法 69 4.5.2 NIOS II軟/硬體整合之韌體設計 72 第五章CAM-based SRAM自我修復系統之驗證與效能測試 75 5.1驗證與測試環境介紹 75 5.2 CAM-based SRAM自我修復系統之驗證與效能評估 77 第六章 結論 95 參考文獻 96

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