NAND 型快閃記憶體有幾個特徵鮮明的特性: 資料不能重複覆寫在相同位置,
除非原先寫入的快閃記憶體塊被抹除。而壽命上的限制是指快閃記憶體的抹除次
數約在10000到100000次，在超過抹除次數後可能會發生寫入錯誤。因為，資料不
能重複覆寫在相同位置，造成寫入時需要先找空的page 寫入新的更新資料，因
此會需要許多額外的抹除，進而會影響系統效能。為了抹除次數減輕問題，針對
快閃記憶體的寫入暫存器被用來把常寫入的資料暫存在暫存器，減少快閃記憶體
上無謂的寫入和刪除。根據我們的觀察，硬體上快閃記憶體的連續塊讀取（page
read cache mode）和平行架構可以提升現有的快閃記憶體的寫入暫存器。我們想
要整合把原先快閃記憶體的寫入暫存器能夠適用在硬體上快閃記憶體的連續塊讀
取（page read cache mode）和平行架構。根據實驗結果，我們的方法可以有效的
提升現有的快閃記憶體的寫入暫存器。

NAND flash memory has very distinct characteristics: the out-of-place update and
the endurance problem. The out-of-place update means that data can’t be overwritten to
the same place unless the residing block is erased first. The endurance problem means that
each flash memory block can endure limited times of erase operations (e.g., 10,000 100,000 times) and could suffer from access errors when beyond the limited times. Therefore, the
out-of-place update can cause a lot of erase operations and damage the system performance.
The endurance problem can damage the lifetime of NAND flash memory.In order
to improve the performance and lifetime of NAND flash memory, a flash-aware write
buffer is used to buffer the frequently accessed data and reduce a lot of write and erase
operations. Based on our observations, we find that the page read cache mode and the
multi-channel I/O parallelism can improve the current flash-aware write buffer schemes.
We want to integrate the concept of the page read cache mode and the multi-channel I/
O parallelism into the design of the flash-aware write buffer schemes. According to the
experimental results, the proposed method can improve the effectiveness of the current
flash-aware write buffer schemes.

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