如同Intel共同創辦人Gordon Moore提出的摩爾定律所描述，積體電路上，可容納的電晶體數目，約每隔兩年便會增加一倍，而這樣成長速度的幕後推手，就是晶片微縮技術所造就的，但傳統金屬氧化物半導體元件在微縮化後會產生一些可靠度的問題，例如短通道效應中的熱載子效應、閘極引起汲極漏電流、汲極與源極的擊穿效應等等，這些對於元件本身電性有非常大的影響，故需要設法解決這些問題。
無接面電晶體因為沒有p型摻雜，無法阻擋汲極與源極之間的擊穿效應(punch through)，故漏電流相較於一般的電晶體來說會有較差的漏電抑制能力，此篇論文的目的就是透過元件結構改變及其相關參數模擬分析，來實踐獲得新型操作方式的高性能元件，故在此提出以溝渠式閘極的無接面電晶體來觸發埋入的雙極性接面二極體，藉此以形成高電流輸出之電晶體；利用溝渠式閘極的方式來改善較差的漏電特性，另外在汲極的區域形成埋入的p型重摻雜區域，藉此會因在汲極區域之p-n接面形成一個能障來抑制漏電流，並且由於上述PN二極體，電流成份不再只有電子流，而且多了電洞流，故總輸出電流提升。所以相較於微縮化之傳統金屬氧化物場效電晶體，此元件結構可有效地改善漏電特性及提高輸出電流。

As described by Moore's Law, proposed by Intel co-founder Gordon Moore, the number of transistors that can be accommodated on an integrated circuit is doubled every two years, and the behind-the-scenes push for such growth is wafer miniaturization. What is created, but the conventional metal oxide semiconductor device will have some reliability problems after miniaturization, such as the hot carrier effect in the short channel effect, the gate leakage current (GIDL), punch through, etc. These have a very large impact on the electrical properties of the components themselves, so it is necessary to try to solve these problems.
Since the junctionless transistor does not have p-type doping to block the punch through, the leakage current has a poor suppression performance compared with the general transistor. The purpose of this paper is to simulate the change of the device structure and its related parameters. This thesis proposes a trench-gate junctionless transistor to trigger the p-n junction diode. The trench-gate is employed to improve poor leakage characteristics, and the embedded p+ region in the n+ drain region can also form an energy barrier to suppress leakage current. In addition, due to the embedded p-n junction diode, the output current is significantly increased. As a result, as compared to the conventional metal oxide field effect transistor with miniaturization, the device structure can effectively improve the leakage characteristics and enhance the output current.

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