本論文共有獨立之兩研究主題。第一部分為「晶片化二維週期性合成傳輸線」之優化設計。該二維週期性合成傳輸線之電路單元方正對稱，可於晶片製程有限空間內進行任意佈局，實現微小化、高佈局密度之微型化電路設計，本論文以前人設計為基礎，進一步提出直通與轉折電路單元分別設計之概念，以實現晶片化二維週期性合成傳輸線之優化設計，使其更加符合設計理念且擁有更良好之響應。吾人進一步運用此二維週期性合成傳輸線實現晶片化枝幹耦合器、鼠境耦合器以及威爾京森分波器等被動射頻電路，經比較後確實擁有更佳之縮小化能力及良好之電氣響應，成功達到優化之目的。
本論文之第二部分，則提出可應用於「反射式信號回溯陣列」之調變機制設計。吾人使用印刷電路板製程，以場效電晶體作為開關，實現二位元相移鍵控調變器，並進一步將其接上枝幹耦合器與延遲線，實現四位元相移鍵控調變器。經實驗驗證其效能，此兩款調變器之位元速率分別可達每秒四百萬位元與每秒八百萬位元，其均方根誤差向量振幅皆於10％左右。最後，吾人將該調變器與前人所設計之反射式信號回溯陣列進行整合，經實驗證實，此調變器不僅不會影響回溯陣列之信號反向傳輸能力，且確實能於信號回傳時將本地資訊透過調變機制送至入射端，其位元速率同樣分別可達每秒四百萬位元與每秒八百萬位元，而均方根誤差向量振幅則皆於12%左右。

This thesis consists of two independent researches. In the first part, an optimization of the two-dimensional periodic synthesized transmission lines is performed using the integrated passive device (IPD) process. Benefitting from the square footprint and symmetrical structure of the proposed unit cell, the two-dimensional synthesized line provides extraordinarily routing flexibility in the layout arrangement. The periodic cells and the corner cells are separately treated to take into account its unique discontinuity effects. An on-chip branch line coupler, rat-race coupler and Wilkinson power divider are developed by using the proposed two-dimensional periodic synthesized lines with not only a substantial reduced size but also good circuit responses.
Secondly, the modulation scheme for a reflection-type retrodirective array (RDA) is studied. A binary phase shift keying (BPSK) modulator is first realized using the field effect transistor (FET) and then integrated with a hybrid coupler to achieve a quadrature phase shift keying (QPSK) modulator. The bit rates of the BPSK and QPSK modulators can, respectively, reach 4 Mbps and 8Mbps while the error vector magnitudes (EVMs) remain about 10%. The developed modulators are directly integrated with a reflection-type RDA to fulfill the design goal. The experiment results validate that the reflection-type RDA with modulators can retransmit the signal back to the incident source with its own information encoded. The measured bit rates of the RDA using QPSK modulators can also reach up to 8 Mbps and the EVM is kept below 13%.

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