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| 研究生： |
黃建棨 Chien-Chi Huang |
|---|---|
| 論文名稱： |
適用於晶片網路系統之基於SDNoC架構的AES加速器 SDNoC-Based AES Accelerator for Network-on-Chip |
| 指導教授： |
阮聖彰
Shanq-Jang Ruan 沈中安 Chung-An Shen |
| 口試委員: |
蘇慶龍
Ching-Lung, Su 呂政修 Jenq-Shiou Leu 沈中安 Chung-An Shen 阮聖彰 Shanq-Jang Ruan |
| 學位類別： |
碩士 Master |
| 系所名稱： |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
| 論文出版年： | 2017 |
| 畢業學年度： | 105 |
| 語文別： | 英文 |
| 論文頁數： | 41 |
| 中文關鍵詞： | 晶片網路 、軟體定義網路 、進階加密標準 、軟體定義晶片網路 |
| 外文關鍵詞： | Network-on-Chip, Software-Defined Networking, Advanced Encryption Standard, Software-Defined Network-on-Chip |
| 相關次數： | 點閱：267 下載：5 |
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晶片網路架構(Network-on-Chip, NoC)以點對點封包架構取代了傳統的匯流排架構，此設計有效地解決了傳統大型系統晶片(System-on-Chip, SoC)內部溝通架構上的瓶頸，因此有越來越多的系統以晶片網路架構來建置。另一方面，隨著資訊安全變得重要，許多系統為了確保資料的安全性與隱密性，會利用加解密演算法將資料內容處理轉換，而進階加密標準(Advanced Encryption Standard, AES)演算法即為目前被廣泛使用的加解密演算法之一。許多系統都加入了加解密的硬體加速器，以加速資料處理的速度。然而，既有的AES硬體加速器皆沒有針對應用於以晶片網路為內部架構的系統所設計。若將目前的AES硬體加速器整合進晶片網路架構中，不僅無法發揮加速器效能，也對整體晶片網路的效率帶來極大的損害。為解決上述之問題，我們提出了一種適用於晶片網路架構中的AES硬體加速器，此加速器為一種多核心的架構設計，以平行運算的方式提升效能，而內部核心間的連結則以軟體定義晶片路架構(Software-Defined Network-on-Chip, SDNoC)來實現。我們所提出的軟體定義晶片網路架構將軟體定義網路 (Software-Defined Networking, SDN)的概念與晶片網路架構結合，相較於傳統的晶片網路，此設計可提升48%的傳輸效能與減少29%功率消耗。此外，因其架構具有可拓展性，此加速器可適用於各種以晶片網路為架構的環境中。
Network-on-Chip (NoC), which is a packet-based and multi-core architecture. It is considered to be a new generation of SoC and the solution for the interconnection problem of large-scale SoCs. Most AES related publications not designed for NoC could suffer the loss of efficiency in either area or performance and cause network congestion if directly porting them to a NoC-based environment. With inspections of resource sharing, packet format, interconnection and operation flow, we propose a Software Defined Network-on-Chip (SDNoC)-based AES accelerator. Our design base on the multicore architecture where the processing elements are interconnected using the SDNoC architecture to improve the efficiency of AES encryption/decryption process in the NoC-based environment. In this design, the processing element which executes AES process are architected. The SDNoC interconnection architecture which is the NoC architecture with the concept of Software-Defined Networking (SDN) can decrease the 48% packet delay and reduce 29% power consumption. With the scalable architecture, the proposed AES accelerator can support various performance demands by simply changing the number of PEs in designs.
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