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| 研究生： |
宋鴻邑 Hung-yi Sung |
|---|---|
| 論文名稱： |
善用固態硬碟之多控制器的平行處理能力 Exploiting Multi-controller Parallelism for Solid-State Drives |
| 指導教授： |
吳晉賢
Chin-hsien Wu |
| 口試委員: |
阮聖彰
Shanq-jang Ruan 陳維美 Wei-mei Chen 林昌鴻 Chang-hong Lin 林淵翔 Yuan-hsiang Lin |
| 學位類別： |
碩士 Master |
| 系所名稱： |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
| 論文出版年： | 2013 |
| 畢業學年度： | 102 |
| 語文別： | 英文 |
| 論文頁數： | 46 |
| 中文關鍵詞： | NAND型快閃記憶體 、固態硬碟 、快閃記憶體轉換層 |
| 外文關鍵詞： | NAND Flash Memory, Solid-State Drives, Flash Translation Layer |
| 相關次數： | 點閱：280 下載：11 |
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NAND型快閃記憶體已被廣泛應用在嵌入式系統和消費電子產品，由於它具有低功耗、快速存取、非揮發性、高抗震等特色。現今，SSD的架構大多採用多控制器架構來處理NAND型快閃記憶體晶片。在傳統多控制器的結構設計 (TMCD) 下，每一個控制器都各自處理自己匯流排上的NAND型快閃記憶體晶片。然而，在並行多控制器的結構設計 (PMCD) 下，任何的晶片將不再侷限於任何特定的控制器，每一個閒置的控制器能透過多控制器架構的設計去存取任何的晶片。在這篇論文中，我們將提出一個新的方法，有效的利用固態硬碟多控制器的平行處理能力。當快閃記憶體轉換層 (FTL) 使用了我們所提出的方法，實驗結果證明，執行時間減少高達5.52％。
NAND flash memory has been widely utilized in embedded systems and consumer electronics, because of its low-power consumption, high-performance access, non-volatility, and shock resistance. Nowadays, the architecture of SSD is using multiple controllers to handle NAND flash memory chips. Under the architecture of traditional multi-controller design (TMCD), one controller can only take responsibility for the specific NAND flash memory chips on its own bus; nevertheless, under the architecture of parallel multi-controller design (PMCD), any controllers can access any NAND flash memory chips on a SSD. In this thesis, we will propose a method to exploit multi-controller parallelism for solid-state drives regardless of TMCD or PMCD. When a flash translation layer (FTL), which provides a block device interface on top of flash memory, adopts the method, the experimental results show that the FTL for multi-controller design could reduce the total response time up to 5.52%.
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