Universal Serial Bus (USB)是一種廣泛應用於電腦系統與外部裝置連接的串列傳輸標準，它擁有著免安裝驅動、易插拔、速度快、相容性高、價格便宜等的優點，至今幾乎已成為電腦與周邊裝置溝通必備的標準介面。實體層是USB架構中最低的一層，為傳輸資料所需的真實連接來建立、維持、拆除，並且提供機械、電子、功能、規範的特性，確保原始資料可在各種實體介質上傳輸。USB 3.1 Gen2的實體層相較於前一代Gen1(舊稱USB 3.0)提供了兩倍的速度達到10 Gbps，並且將原本的8b/10b編碼改成128b/132b編碼，減少84%的冗碼率(Overhead)以增加資料的吞吐量(Throughput)。
本篇論文中的實體層傳輸端，利用平行化的擾碼器(Scrambler)降低Core Clock時脈，來減少87.9%的功率消耗，設計的編碼器錯開讀寫的時間，大量節省所需的正反器從264個降至20個；接收端的資料對齊器使用移位暫存器(Shift Register)來儲存並判斷，並且利用半滿技術實現彈性緩衝器(Elastic Buffer)解決時鐘相位偏差的問題，最後也利用平行化的解擾碼器使接收的資料與傳輸一致。
完成的電路符合USB 3.1 Gen2 的傳輸規範，使用Xilinx的Virtex 6的xc6vcx75t-2ff484實現。發送端共用消耗了322個查找表(Look up table, LUT)和130個正反器(Flip-Flop, FF)，操作時脈可到86.6 MHz，位元時脈則可到714.3 MHz。接收端共消耗了1867個查找表和977個正反器，操作時脈可到67.3 MHz，位元時脈則可到555.6 MHz。

Universal Serial Bus (USB) is a serial transmission standard widely used in computer systems and external devices. It has many advantages such as driverless installation, easy insertion and removal, fast speed, high compatibility, and low price. Most of computers and peripheral devices choose USB as the standard interface due to these advantages. The physical layer is the lowest layer in the USB architecture. It is built, maintained, and removed for the real connections. To ensure that raw data can be transmitted over a variety of physical media, the physical layer provides mechanical, electrical, functional, and specification features. USB 3.1 Gen2 provides twice the speed compared to the previous generation Gen1 (as known as USB 3.0), and changes the 8b/10b encoding to 128b/132b encoding, which greatly reduces the redundancy up to 84%, thereby increasing the data throughput.
In the thesis, the transmitter uses a parallel scrambler to reduce power consumption by 87.9%. The designed encoder separates the reading and writing actions, and reduces a large number of flip-flops (FFs) from 264 to 20. At the receiver, the data aligner uses a shift register to store and monitor data. To solve the difference between the symbol clock and core clock, a half-full technique is applied to the elastic buffer. Moreover, the parallel descrambler makes the received data identical with the transmitted data.
The completed circuit complies with the USB 3.1 Gen2 transmission specification and is implemented using Xilinx's Virtex 6 xc6vcx75t-2ff484. The transmitter consumes 322 lookup tables (LUTs) and 130 FFs. The maximum operating frequency of the core clock is 86.6 MHz and the bit clock is 714.3 MHz. The receiving end consumes 1867 LUTs and 977 FFs, the operation clock can reach 67.3 MHz, and the bit clock can reach 555.6 MHz.

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