本論文針對 MIMO OFDM系統提出Maximum-logarithm(Max-log) Maximum A Posteriori Probability (MAP)檢測器演算法之設計與實現，我們分別比較Zero-Forcing(ZF)與Max-log MAP兩種不同的演算法於Rayleigh fading channel的SISO模式和MIMO模式下的封包錯誤率。在SISO模式時，由於通道係數只有傳送端天線1對上接收端天線1，並不會受到其他天線干擾，故兩種演算法在模擬結果上差異不大，然而在 MIMO模式時，傳送端天線1及天線2的資料會因為通道而互相影響再加上多路徑散射的影響的情況下傳至接收端天線1及天線2，通道的情況會比SISO模式時更加複雜許多。從模擬結果可得知，在MIMO模式時，Max-log MAP演算法在封包錯誤率上的表現比ZF演算法好上許多，但是在硬體實現電路的面積上，由於Max-log MAP演算法所使用的邏輯數量比ZF演算法還要多，故面積相對的也大了一些。本論文以實現Max-log MAP演算法為目標，並採用Verilog硬體描述語言設計，利用Xilinx ISE進行合成，最後將電路實現於FPGA開發板上。

This thesis proposes the design and implementation of a Maximum-logarithm (Max-log) Maximum A Posteriori probability (MAP) detection algorithm for MIMO-OFDM systems. We compare the packet error rates of the Zero-Forcing (ZF) algorithm and Max-log MAP in SISO and 2x2 MIMO configurations with Rayleigh fading channel. In SISO configuration, since there is only one antenna at the transmitter and at the receiver, there is no interference and the difference in performance of both algorithms is not significant. In 2x2 MIMO configuration there is mutual interference between both transmit antennas, and the information is transmitted along the multipath fading channel to two receive antennas. Hence the channel conditions are more complex than in the case of SISO. Simulation results show that in MIMO configuration the packet error rate of Max-log MAP is much better than ZF. However, since the logic count of Max-log MAP is higher than ZF, the circuit area required by Max-log MAP is also higher. In this thesis, using Verilog HDL for design and Xilinx ISE for circuit synthesis, we implement the Max-log MAP algorithm on an FPGA development board.

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