在現今的動態影像壓縮技術中，MPEG-4已經漸成為主流，而且廣泛的被應用在各種多媒體產品上，因此如何設計出有效率之MPEG-4編碼器成為值得研究的課題。本論文提出使用硬體實現之MPEG-4 simple profile視訊編碼器，主要的硬體模組包含動態預估(Motion Estimation)模組，離散餘弦轉換(DCT)模組，DC預測(DC Prediction)模組，可變長度編碼(Variable Length Coding)模組等。

在動態預估方面，提出一種有效的硬體架構與流程以實現三步驟搜尋演算法，並利用FPGA晶片內部之記憶體區塊來儲存所需之参考資料，可以有效減少硬體面積。在離散餘弦轉換方面，採用管線式的架構實現Loeffler之快速一維DCT演算法，使用FPGA晶片內之DSP區塊以實現快速之乘法器，並使用矩陣轉置緩衝器合併兩個一維DCT成為二維的DCT模組。在直流預測方面，使用規則之暫存器串列來儲存需要參考的直流值，可以有效減少控制的複雜度，同時和DCT及量化(Quantisation)模組整合以完成快速之轉換編碼(Transform Coding)流程。在整合上述之硬體模組設計出的編碼器，可以將視訊序列編碼成MPEG-4 Simple Profile之格式。

The emerging MPEG-4 becomes the main standard of the video compression, and applies in many multimedia products. Therefore, how to design an efficiently MPEG-4 video encoder becomes the important topic. This thesis presents the hardware architecture design for MPEG-4 video coding system. Key modules include motion estimation, motion compensation, DCT, DC prediction and entropy coding.
The proposed efficient architecture uses three-step block matching motion estimator, and utilize the embedded RAM on FPGA to reduce hardware size. The transform coding module use pipeline architecture to calculate coefficients, which integrate two Loeffler fast 1-D DCT into 2-D DCT module. The DC prediction module uses 4-block shift registers to store DC coefficients and generate predictor; its regularity can simplify control path and reduces memory access time. Our integrated coding system can encode well-known video sequences into MPEG-4 simple profile bitstream. We use software MPEG-4 decoder to verify our encoded bitstream and the test show our system work.

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