用於高速時間交錯類比數位轉換器之時脈校正處理器設計

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研究生：	胡嘉翊 Jia-Yi Hu
論文名稱：	用於高速時間交錯類比數位轉換器之時脈校正處理器設計 Design of a Timing Skew Calibration Processer for High-speed Time-interleaved ADCs
指導教授：	鍾勇輝 Yung-Hui Chung
口試委員:	陳亮仁 Liang-Jen Chen 陳伯奇 Po-ki Chen 曾偉信 Wei-Hsin Tseng 范振麟 Jen-Lin Fan 鍾勇輝 Yung-Hui Chung
學位類別：	碩士 Master
系所名稱：	電資學院 - 電子工程系 Department of Electronic and Computer Engineering
論文出版年：	2018
畢業學年度：	106
語文別：	中文
論文頁數：	110
中文關鍵詞：	類比數位轉換器、時脈歪斜、延遲鎖定迴路、時間交錯
外文關鍵詞：	ADCs, Skew, Delay lock loop, Time-interleaved
相關次數：	點閱：260 下載：8
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本論文著重於高速時間交錯類比數位轉換器的時脈歪斜校正技術研發。時間交錯類比數位轉換器是由多個單通道類比數位轉換器組成。由於單通道類比數位轉換器受限於CMOS製程技術，當其取樣頻率無法滿足功耗與取樣頻率成線性關係時，則可使用時間交錯的架構，讓取樣率與通道數呈倍數關係。但時間交錯的架構會衍生出通道之間的取樣時間不一致的問題，嚴重地影響著高頻輸入訊號的表現。因此本論文提出了一個新的時脈歪斜校正技術，用以解決通道之間的取樣時間不一致的問題。
相較於其他的時脈歪斜校正技術，本論文所提出的時脈歪斜校正技術，其演算法之硬體實現成本較低。在時脈校正部分，只需額外的數位控制延遲電路。在時脈歪斜偵測部分，則使用加法器來取代乘法器，大量降低在硬體上的複雜度與設計上的困難度。在行為分析模擬(使用MATLAB模擬)中，已驗證本演算法的可行性。因此，我們進一步在硬體實現。利用55奈米低功耗CMOS製程實現了一個八位元、每秒五千兆赫的時間交錯類比數位轉換器，其面積晶片為4.84平方毫米。

This thesis focuses on researching and developing in timing skew calibration of high-speed time-interleaved (TI) ADCs. The operating speed of single-channel ADCs are limited by CMOS process technologies. When the sampling frequency cannot meet the increase in the linear relationship between power consumption and sampling frequencies, the time-interleaved operation can be used to achieve a low power demand. But the time-interleaved architecture derives the problem of inconsistent sampling times between channels, seriously affecting the performance of high-frequency input signals. Therefore, this paper presents a new clock skew correction technique to solve the problem of inconsistent sampling time between channels.
Compared with other clock skew correction schemes, this thesis proposed the clock skew correction technology. The hardware cost of the proposed skew calibration algorithm is lower than prior works. In the clock correction section, only an additional digital control delay circuit is required. In the clock skew detection section, the adder is used instead of the multiplier, which greatly reduces the complexity and design difficulty on the hardware. In the behavioral simulation and analysis (using MATLAB simulation), the feasibility of this algorithm has been verified. As a result, we have implemented an 8-bit 5-GS/s TI-ADC in a 55nm low-power CMOS process with a chip area of 4.84 square millimeters.

論 文 摘 要    i
Abstract    ii
誌 謝    iv
Contents    vi
List of Figures    x
List of Table    xiv
Chapter 1    Introduction    1
1    Background Survey    3
1.1    Cross Correlation Estimation Scheme    4
1.2  Comparison of Autocorrelation Estimation Schemes    7
1.3  Delta-Sampling and Interpolation    9
2  Motivation    12
3  Organization of the Thesis    13
Chapter 2    Errors of Time-Interleaved ADCs    14
1  Time-Interleaved ADCs    14
2  Static Errors of Time-Interleaved ADCs    17
3  Timing Errors of TI ADCs    18
3.1  Description of Skew and Jitter    18
3.2  ENOB Degradation vs. Skew    20
3.3  ENOB Degradation vs. Jitter    21
4  Summary    23
Chapter 3    Proposed Skew Calibration Scheme    26
1  Basics of the Skew Sensor    26
1.1  Introduction of Autocorrelation Function    26
1.2  Limitations of the Autocorrelation Function    27
1.3  Skew Estimation in TI ADCs    29
1.4  Detection Failures of Autocorrelation Function    30
1.5  Simple Model of the Autocorrelation Model    37
2  Introduction of the Proposed Skew Calibration Scheme    39
3  Variance Convergent Procedure    42
3.1  Concept of Variance Convergent Procedure    42
3.2  Comparison of Timing Space and Convergence Direction    43
3.3  Algorithm of Variance Convergent Procedure    45
3.4  Steady State of the Variance Convergent Procedure    46
4  Reference Convergent Procedure    48
4.1  Concept of the Reference Convergent Procedure    48
4.2  Algorithm of the RCP Scheme    50
5  The Skew Calibration Model    51
5.1  Implementation of the Proposed Calibration Algorithm    51
5.2  Skew Calibration Processer    53
6  Simulation Results of the Proposed Calibration Processor    54
6.1  Implementation of the Proposed Calibration Algorithm    54
6.2  Calibration with and without the Digital Filter    62
Chapter 4    ADC Architecture and Circuit Implementation    64
1  An 8-bit TI ADC Architecture    64
2  Delay-Locked Loop (DLL)    66
2.1  Operation of the DLL    66
2.2  Phase Detector (PD)    68
2.3  Charge Pump (CP)    69
2.4  Voltage Control Delay Line (VCDL)    72
2.5  Phase Offset and Skew    74
2.6  Proposed DLL Architecture    75
3  Digital Control Delay Line (DCDL)    77
3.1  Operation of the DCDL    77
3.2  Analysis of the DCDL    78
3.3  Proposed DCDL    80
4  Digital TUNER    81
4.1  Operation of the Digital TUNER    81
4.2  Accumulator    84
5  Downsample Circuit    86
5.1  Operation of the Downsample Circuit    86
5.2  Frequency Divider    87
Chapter 5    ADC Layout and Simulation Results    90
1  DLL    90
2  DCDL    94
3  TUNER    96
3  Downsample Circuits    98
3  8-bit TI ADC    100
Chapter 6    Conclusions and Future Works    105
1  Conclusions    105
2  Future Works    106
Reference    107
Appendix A    109

                                

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