爐管為半導體產業經常使用的製程設備，其產能及良率為半導體市場之技術指標，因此本研究提出8吋垂直式爐管之流場數值模擬，評估流場對於氧化製程所產生的影響，再藉由實驗結果的比對，找出流場與良率的相關性，在目前爐管設計的現場量測結果中最大的缺失在於，爐管內放置了150片的晶圓進行氧化製程，但前30片的晶圓的氧化層厚度不均而無法使用，因此本研究針對爐管之流場進行模擬分析，試找出流場與氧化製程關係。首先藉由通入之氧氣與氫氣體質量流率，計算出化學反應後產生的水蒸氣質量流率，並做為入口之邊界條件，在完成模擬後，利用後處理觀察爐管各區域的流場分佈，找出流場的缺失，除此之外，為針對晶圓做觀察，本研究監控每片晶圓之間的流入速度，以計算流入晶圓之流量，觀察整批晶圓的流量分佈，進行評估可能的原因後，設計不同參數之模型進行參數化模擬，找出各參數對流場的影響，最後設計出符合成本考量與良率要求之爐管模型。在改變了Shower Head外圈孔洞的數量後，可發現當增加外圈孔洞數時，流場的均勻度可有效的提升，而孔洞的數量增加到64孔時，晶圓區域的大型渦旋也完全消除，而當孔洞數量減少到完全沒有外圈孔洞時，也可得到同樣的效果，因此可發現Shower Head外圈孔洞所產生的噴流為渦旋生成的重要因素，且在改變了晶舟擋板與晶圓的間距時發現到渦旋的大小與成長空間的限制關係，雖然模擬中並未考慮化學反應，且溫度均勻，但對於流場特性與幾何參數作詳細的研究，對於流場均勻化的改良還是有很大的成果。

Furnace is the most essential and extensively used equipment in the semiconductor factory, while the production capacity and its yield rate are the key technical and profitable indicators for the semiconductor industry. To reduce the cost, overloading the wafers into the furnace becomes a popular choice for many Fabs; however, this approach may change the flow patterns inside the furnace and usually downgrade the yield rate of product significantly. Therefore, this study intends to establish the capability for simulating the flow field associated with the oxidation process inside an 8-inch vertical furnace. At first, the calculated flow pattern is analyzed carefully and correlated with the distribution uniformity of coating thickness over the entire 150 wafers, which are attained through the inspection on an actual oxidation process. Clearly, this comparing effort reveals that a strong correlation existed between the region of adverse flow and the location of uneven-coating wafers, which are the top 30 wafers in the carrier. This fact confirms and motivates this research to improve the yield rate by diminishing the adverse flow pattern inside the furnace.
In addition, CFD flow visualization shows that these vortices locate mainly under the holes on the shower head, which is designed for spreading out the reaction gas to the wafer layers in downstream. The gas emitting through the hole forms a jet flow and thus creates a big velocity gradient needed for generating the vortex. Also, the distance between holes provides the developing zone for vortex formulation. Thus, diminishing the jet streams and the associated vortices near the shower head are identified as the effective approach to increase the yield rate.
Thereafter, two alternatives, adding extra holes on the shower head and enlarging the distance between shower head and wafers carrier, are proposed and validated numerically to eliminate these vortices successfully. The increasing holes on the shower head can generate more vortices with a smaller size, which becomes almost negligible for the case of shower head with 64 holes. Moreover, these vortices can develop freely and diminish when a sufficient distance from the wafer carrier is maintained while the available space to locate wafers also decreases. Thus, it is concluded that adding holes on the shower head is an appropriate solution for increasing the yield rate of wafer fabrication. In summary, this work successfully establishes a numerical model and a systematic procedure for correlating the flow pattern to the coating uniformity on the wafer. Note that this rigorous analysis scheme can be used to improve the wafer production in other furnaces used in semiconductor process.

[1] 張勁燕，“半導體製程設備”，五南圖書出版，2009年。
[2] 國立中山大學，環境科技課程之媒體網路化，http://www2.nsysu.edu.tw/IEE/lou/。
[3] Perter Van Zant, “Microchip fabrication : a practical guide to semiconductor processing, ” McGraw-Hill,2001.
[4] Pradip K. Roy, Sailesh M. Merchant and Sanjeev Kaushal, “Thermal Processing in Fast Ramp Furnaces,”Journal of Electronic Materials, Vol. 30, No. 12, pp. 1578-1583, 2001.
[5] Jimmy Hashem and Brian Bradshaw, “The Practical Use of Residual Gas Analysis In a Semiconductor Thermal Processing Module,” Institute of Electrical and Electronics Engineers, IEEE, pp. 421-424, 08 Oct 2001-10 Oct 2001.
[6] Rajendra Singh, Mohammed Fakhruddin and Kelvin F. Poole, “The impact of single-wafer processing on semiconductor manufacturing,“Institute of Electrical and Electronics Engineers, IEEE, Vol. 16, No. 2, pp. 96-101, May 2003.
[7] 范躍鐘，“氮化處理對閘極介電層二氧化鉿與矽晶圓之電漿蝕刻製程研究”，國立清華大學電子儀控組碩士論文，2006年。
[8] Anjuli T. Appapillaia and Emanuel M. Sachs, “A method for temperature profile measurement of silicon wafers in high-temperature environments,” American Institute of Physics, AIP, Vol. 109, No. 3, 2011.
[9] Kouhei Ehara, “Thermal Oxidation Due to Air Back-Diffusion in Horizontal Furnaces,“The Electrochemical Society, Vol. 144, No. 1, January, pp. 326-334, 1997.
[10] 林獻堂，“快速熱氧化製程氧化層厚度均勻性之研究”，國立成功大學航空太空工程研究所碩士論文，2005年。
[11] Casey Barker, Al Badowski, Bruce Whitefield, Keith L. Levien, and Milo D. Korestky, “Factors Affecting Thickness Variation of SiO2 Thin Films Grown by Wet Oxidation,” Institute of Electrical and Electronics Engineers, IEEE, Vol. 24, No. 2, pp. 348-357, May, 2011.
[12] Yuan Feng, Guojun Liu, Changling Yan , Yongqin Hao, Yong Wang, Peng Lu, Yang Li and Zaijin Li, “The Law of Wet Oxidation Rate in 850nm VCSELs,” Photoelectronic Technology Committee of the Chinese Society of Astronautics, SPIE Vol. 9521, 2015.
[13] A. Iagar, I. Sora, D. Radu, C. Panoiu and C. Abrudean, “Technological practicability of the numerical modeling of induction heating process in steel pieces,” Revista de Metalurgia, Vol. 45(1), pp. 20-31, 2009.
[14] 李淙賢，“直立式爐管之晶圓裝載區域的流場模擬分析”，國立台灣科技大學機械工程系碩士論文，2011年。
[15] E. Hachem, G. Jannoun, J. Veysset, M. Henri, R. Pierrot, I. Poitrault, E. Massoni and T. Coupez, “Modeling of Heat Transfer and Turbulent Flows Inside Industrial Furnaces,” Simulation Modelling Practice and Theory, Vol. 30, pp. 35-53, January 2013.
[16] Xing Huang, Wei Qian , Wei Wei , Jingning Guo and Naitao Liu, “3D numerical simulation on the flow field of single tuyere blast furnaces A case study of the Shuiquangou iron smelting site dated from the 9th to 13th century in China,” Archaeological Science, Vol. 63, pp. 44-58, November 2015.
[17] 周欣怡，“晶圓快速熱製程爐之設計”，國立屏東科技大學機械工程系碩士論文，2000年。
[18] 馬梓晏，“快速熱處理爐內流場、溫度場及應力場之穩態解”，國立台灣科技大學機械工程系碩士論文，2003年。
[19] 洪順清，“全模式快速熱製程反應爐之溫度控制”，國立屏東科技大學車輛工程系碩士論文，2004年。
[20] 李岱柏，“高溫石墨純化爐熱場設計與分析”，國立台灣科技大學機械工程系碩士論文，2014年。
[21] Jim Griffin and Ron Bowman, “Practical IC Fabrication,” Integrated Circuit Engineering Corporation,1990.
[22] 義守大學線上學習資源，http://www.isu.edu.tw/upload/81201/43/news/postfile_11051.pdf
[23] 蕭宏，“半導體製程技術導論”，全華出版社，2014年
[24] 台灣富創得工程股份有限公司，http://www.fortrend.com.tw/
[25] 東京威力Tokyo Electron Limited，http://www.tel.com/tet/
[26] B. E. Launder and D. B. Spalding, “Lectures in Mathematical Models of Turbulence,”Academic Press,1972.
[27] Patankar, S. V. and Spalding, D. B., “A Calculation Procedure for Heat Mass and Momentum Transfer in Three-Dimensional Parabolic Flows,” International Journal of Heat Mass Transfer, Vol. 15, pp. 1787-1806, 1972.