對於十六位元連續漸進式類比數位轉換器(SAR ADC)來說，雜訊與線性度是晶片實現的兩個主要難題。雜訊部分由於缺乏超取樣(Oversampling)與雜訊整形(Noise-shaping)等機制，主要是藉由電路設計技巧來滿足雜訊的規格。在線性度方面，主要是受到電容不匹配的影響。在本論文中，使用兩種技術來改善線性度：一是二階電容交換技術，另一是快速二元視窗切換技術。二階電容交換技術是將前兩次切換所使用的電容，利用交換機制將失真轉變成雜訊，以得到更好的無雜散動態範圍(SFDR)。快速二元視窗切換技術則是改變傳統連續漸進式類比數位轉換器的電容切換方式，藉由減少不必要的電容切換來改善訊號對雜訊與失真比(SNDR)。
在台積電的0.18微米CMOS製程之下，實現了一個十六位元，每秒一百萬次取樣之免校正連續漸進式類比數位轉換器，晶片面積為0.52 平方毫米。在1.8伏特的操作電壓之下，消耗的功率是1.54毫瓦。當使用一千赫茲的弦波作為輸入訊號時，量測到的微分非線性誤差(DNL)為-0.7/1.3 LSB，積分非線性誤差(INL)為-3.1/3.3 LSB。量測到的訊號對雜訊與失真比是76.3dB，無雜散動態範圍是102dB，性能指標(FOMS)是161.4 dB。

For 16-bit successive approximation register (SAR) analog-to-digital converters (ADCs), noise and linearity are two major challenges for chip implementation. In this work, without the oversampling and noise-shaping techniques, I use several circuit design skills to meet the noise specification. For the linearity, it’s mainly affected by the capacitor mismatch. In this thesis, two techniques are presented to improve the ADC linearity. One is the level-two capacitor-swapping technique, and the other is the fast-binary-window DAC switching scheme. For the first two MSB capacitor switching, the level-two capacitor-swapping utilizes the swapping mechanism to transform the distortion into noise for better SFDR. The fast-binary-window DAC switching technique changes the SAR ADC’s conventional switching method to improve SNDR by reducing unnecessary capacitor switching.
A 16-bit 1-MS/s calibration-free SAR ADC was implemented in TSMC 0.18μm CMOS. This ADC chip occupies die area of 0.52 mm2. It consumes 1.54 mW from a 1.8V supply. At a 1-kHz input frequency, the measured DNL is -0.7/1.3 LSB. The measured INL is -3.1/3.3 LSB. The measured SNDR and SFDR are 76.3 dB and 102 dB, respectively. This leads to a Schreier FOM of 161.4 dB.

[1]J. A. McNeill, et al., "All-Digital Background Calibration of a Successive Approximation ADC Using the “Split ADC” Architecture," IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 58, no. 10, pp. 2355-2365, Oct. 2011.
[2]Y. Chi and D. Li, "A 1.8 V 1.1 MS/s 96.1 dB-SFDR successive approximation register analog-to-digital converter with calibration," in Journal of Semiconductors, vol. 34, no. 4, pp. 1-7, Apr. 2013.
[3]A. Bannon, et al., "An 18 b 5 MS/s SAR ADC with 100.2 dB Dynamic Range," in VLSI Symp. on Circuits, June 2014, pp. 1-2.
[4]J. Shen, et al., “A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS,” IEEE J. Solid-State Circuits, vol. PP, no. 99, pp. 1-12, Jan. 2018.
[5]H. Li, et al., “Signal-Independent Background-Calibrating 20b 1MS/s SAR ADC with 0.3ppm INL,” in Proc. of IEEE ISSCC, Feb. 2018, pp. 242-243.
[6]C.-C. Liu, et al., "A 12 bit 100 MS/s SAR-Assisted Digital-Slope ADC," in IEEE Journal of Solid-State Circuits, vol. 51, no. 12, pp. 2941-2950, Dec. 2016.
[7]D. A. Johns and K. Martin, Analog Integrated Circuit Design. New York, NY, USA: Wiley, 1997, ch. 13, sec. 1, pp. 487–489.
[8]Y.-H. Chung, M.-H. Wu, and H.-S. Li, “A 12-bit 8.47-fJ/conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS,” IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 62, no. 1, pp. 10-18, Jan. 2015.
[9]Y.-H. Chung, C.-W. Yen, P.-K. Tsai, and B.-W. Chen, “A 12-bit 40-MS/s SAR ADC With a Fast-Binary-Window DAC Switching Scheme, ”IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1-10, July 2018.
[10]B.-S. Song et al., “A 1 V 6 b 50 MHz current-interpolating CMOS ADC,” in Symp. VLSI Circuits, 1999, pp. 79-80.
[11]M. Miyahara, Y. Asada, D. Paik, and A. Matsuzawa, “A low-noise self- calibrating dynamic comparator for high-speed ADCs,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2008, pp. 269–272.
[12]C. C. Liu, S. J. Chang, G. Y. Huang, Y. Z. Lin, C. M. Huang, C. H. Huang, L. Bu, and C. C. Tsai, “A 10 b 100 MS/s 1.13 mW SAR ADC with binary-scaled error compensation,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2010, pp. 386–387.
[13]Y. Zhu, C. Chan, S. Sin, S. U, R. Martins, and F. Maloberti, “A 10-bit 100M-S/s reference-free SAR ADC in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1111–1121, Jun. 2010.
[14]C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 10-bit 50 MS/s SAR ADC with a monotonic capacitor switching procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731–740, Apr. 2010.
[15]S.-W. M. Chen and R. W. Brodersen, “A 6-bit 600 MS/s 5.3 mW asynchronous ADC in 0.13- μ m CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2669–2680, Dec. 2006.
[16]M. Dessouky and A. Kaiser, “Very Low-Voltage Digital-Audio Σ∆ Modulator with 88-dB Dynamic Range Using Local Switch Bootstrapping,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 349–355, Mar. 2001.
[17]A. H. T. Chang, “Low-Power High-Performance SAR ADC With Redundancy and Digital Background Calibration,” Ph.D. dissertation, Dept. Elect. Eng. Comput. Sci., Massachusetts Inst. Technol., Cambridge, MA, USA, 2013.
[18]M. Maddox, B. Chen, M. Coln, R. Kapusta, J. Shen, and L. Fernando, “A 16 bit linear passive-charge-sharing SAR ADC in 55 nm CMOS,” in IEEE Asian Solid-State Circuits Conf. (A-SSCC) Tech. Papers, Nov. 2016, pp. 153–156.