在無線通訊系統中，頻率合成器是用來做訊號頻率的升降之用。在頻率合成器電路裡，壓控振盪器與除頻器是重要的核心電路之ㄧ。對壓控振盪器而言，必須提供低相位雜訊的輸出，以避免相鄰雜訊訊號經由混波轉換產生干擾。。而振盪器的輸出則經由除頻器來達成降頻的工作，因此，除頻器需具有高頻操作、寬的操作頻寬及低功率消耗。
本論文提出一個三相位電壓控制振盪器和兩個四相位壓控振盪器。在第一個電路裡，它是個使用三推式耦合的三相位互補式考畢茲壓控振盪器。第二個電路是個使用環型電感技術完成的四相位壓控振盪器。第三個電路中，我們提出一個使用 P型電晶體共閘極耦合技術產生四相位輸出的壓控振盪器。
首先，一個5.3GHz的壓控振盪器使用台積電0.35微米製程實現三相位且在平衡的電路架構中使用三個相同的單端互補式考畢茲壓控振盪器和透過打線的電感效應耦合成三相位輸出。三相位壓控振盪器操作頻率從5.15 GHz 到 5.45 GHz且功率消耗為4.34 mW。而在輸出頻率為5.37 GHz時，1 MHz偏移頻率下相位雜訊為 -119.18 dBc/Hz，晶片面積0.82 × 0.636 mm2 且figure of merit為 -187.5 dBc/Hz。
其次，一個四相位壓控振盪器使用閉迴路環型電感架構且由台積電90 奈米製程技術製作完成。此四相位壓控振盪器頻率操作在7.05 GHz 至 8.15 GHz。而在輸出頻率為8.15 GHz時，1 MHz偏移頻率下相位雜訊為 -119.98 dBc/Hz。此電路之供應電壓為0.85 V時，電流為4.2 mA、消耗功率為3.57mW。
最後，我們提出新的四相位壓控振盪器，將兩組n型交錯耦合電晶體為核心，透過P型電晶體為共閘極放大器和尾端變壓器當作耦合元件實現四相位輸出。此電路的可調頻率為6.47 GHz 至7.71 GHz。而在輸出頻率為7.43 GHz時，1 MHz偏移頻率下相位雜訊為 -116.01 dBc/Hz且消耗功率為2.7mW。此電路的figure of merit為 -189.12 dBc/Hz。

In wireless communication system, frequency synthesizers are used to implement the frequency up/down converting of signal. In a frequency synthesizer, voltage-controlled oscillator (VCO) and divider are the key blocks. For VCOs, low phase-noise output is required to avoid corrupting the mixer-converted signal by close interfering tones. The output of the VCO is divided down by the frequency divider which requires operating at high frequencies, wide operating range and lower power consumption.
We present a three-phase VCO and two Quadrature VCOs in this thesis. In the first circuit, it’s a three-phase complementary colpitts VCO using the triple-push coupling. The second circuit is a Quadrature VCO using ring inductor technique. In the third circuit, we proposed a VCO which provides quadrature outputs by PMOSFET common-gate -coupling technique.
Firstly, a prototype 5.3 GHz VCO in 0.35 μm CMOS process is proposed to generate 3 output phases and it uses three identical single-ended complementary Colpitts VCOs in a balanced configuration and coupled via the bonding inductors to provide 3-phase outputs. The 3-phase VCO oscillates from 5.15 GHz to 5.45 GHz and the power consumption is 4.34 mW. The phase noise is -119.18 dBc/Hz at 1 MHz offset frequency from 5.37 GHz. The VCO occupies a chip area of 0.82 × 0.636 mm2 and provides a figure of merit of -187.5 dBc/Hz.
Secondly, a QVCO uses a closed-loop ring inductor and is implemented in a standard TSMC 90 nm 1P9M CMOS technology. This QVCO operates between 7.05 GHz and 8.15 GHz. The measured phase noise of the VCO operating at 8.15 GHz is -119.98 dBc/Hz at 1 MHz offset while the QVCO draws 4.2 mA and 3.57 mW consumption from a supply voltage of 0.85 V.
Finally, we presents a new quadrature voltage-controlled oscillator (QVCO), which consists of two n-core cross-coupled voltage-controlled oscillators (VCOs) with pMOSFET common-gate amplifiers and tail transformers as coupling devices. The free-running frequency of the QVCO is tunable from 6.47 GHz to 7.71 GHz . The measured phase noise at 1 MHz frequency offset is -116.01 dBc/Hz at the oscillation frequency of 7.43 GHz and the total power consumption is 2.7 mW, the figure of merit (FOM) of the proposed QVCO is -189.12 dBc/Hz.

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