近年來互補式金氧半導體製程技術的快速成長，使得超大型積體電路之工作時脈頻率快速增加。在高速的同步系統中，時脈偏移所造成的時脈不同步現象，將嚴重影響系統工作的正確性，因此，時脈校正電路之重要性不言可喻。大多數的時脈訊號皆由延遲鎖定迴路或鎖相迴路所產生，然而，延遲鎖定迴路容易設計及較為穩定的特性，讓延遲鎖定迴路比鎖相迴路更廣泛的應用在時脈誤差的調整上。同時，延遲鎖定迴路較鎖相迴路提供更好的抖動效能。
本論文提出以一組數位控制延遲元件搭配循序漸近暫存器電路所組成的延遲鎖定迴路，來達到自我相位校正的功能，改善傳統式延遲鎖定迴路易受製程、電壓和溫度的影響的缺點，並達到低抖動的效能。
低抖動電流式循序漸近校準延遲鎖定迴路所使用製程為TSMC 0.18-μm 1P6M，主要動作電路晶片面積為210μm×110μm。依據量測結果可得知本電路操作頻率範圍為1-1.45 GHz，最大功率消耗為45.9 mW。當操作頻率在1.45 GHz時，所量測到的峰值對峰值抖動和均方根抖動分別為10.8 ps與1.586 ps。

The unstoppable improvement of CMOS process technology makes the Very Large Scale Integration (VLSI) systems operate at a higher and higher frequency in recent years. For high speed communication systems, the clock skews may make the system out of synchronization and thus deteriorate the system performance seriously. As a result, clock alignment circuits based on delay-locked loops (DLL) or phase-locked loops (PLL) are required to conquer the above problem. However, Delay-locked loops are more attractive for clock-deskew than phase-locked loops due to easy design and excellent stability. Additionally, delay-locked loops usually offer better jitter performance than phase-locked loops.
A novel delay-locked loop with modified delay cells and successive approximation register bias current adjustment is proposed in this thesis to enhance jitter performance and reduce process, voltage and temperature (PVT) sensitivities.
The proposed circuit is realized in TSMC 0.18-μm 1P6M standard CMOS process and owns a chip area of 210μm×110μm. The operation frequency range of the delay-locked loop is verified to be 1-1.45 GHz by measurements and the maximum power consumption is confirmed to be 45.9 mW. At 1.45 GHz operation frequency, the measured peak-to-peak rms jitters are 10.8 ps and 1.586 ps respectively.

[1] M. Johnson and E. Hudson,“ A variable delay line PLL for CPU- coprocessor synchronization”, IEEE Journal of Solid-State Circuits, vol. 23, pp. 1218-1223, Oct. 1988.
[2] T. H. Lee, K. S. Donnelly, and J. T. Ho et al., “ A 2.5V CMOS Delay-Locked Loop for 18 Mbit, 500 Megabyte/s DRAM”, IEEE Journal of Solid-State Circuits, vol. 29, no. 12, pp. 1491-1496, Dec. 1994.
[3] Y. Moon, J. Choi, K. Lee, D. Jeong, and M. Kim, “ An All-Analog Multiphase Delay-Locked Loop Using a Replica Delay　Line for Wide-Range Operation and Low-Jitter Performance", IEEE Journal of Solid-State Circuits, vol. 35, pp. 377-384, Mar. 2000.
[4] B.-S. Kim and L.-S. Kim, “ A Low Power 100MHz All Digital Delay-Locked Loop”, IEEE International Symposium on Circuit and System, pp. 1820-1823, Jun. 1997.
[5] Y. Okajima, M. Taguchi, M. Yanagawa, K. Nishimura, and O. Hamada, “ Digital Delay Locked Loop and Design Technique For High-Speed Synchronous Interface”, IEICE Trans. Electron., vol. E79-C, no. 6, pp. 798-807, Jun. 1996.
[6] M. Hasegawa, M. Nakamura, S. Narui, S. Ohkuma and Y. Kawase et al., “ A 256-Mb SDRAM Using a Register-Controlled Digital DLL”, IEEE Journal of Solid-State Circuits, vol. 32, no. 11, pp. 1728-1734, Nov. 1997.
[7] F. Lin, J. Miller, A. Schoenfeld, M. Ma, and R. J. Baker, “ A Register-Controlled Symmetrical DLL for Double-Data-Rate DRAM,” IEEE Journal of Solid-State Circuits, vol. 34, pp. 565-568, Apr. 1999.
[8] G.-K. Dehng, J.-M. Hsu, C.-Y. Yang, and S.-I. Liu, “ Clock-Deskew Buffer Using a SAR-Controlled Delay-Locked Loop”, IEEE Journal of Solid-State Circuits, vol. 35, pp. 1128-1136, Aug. 2000.
[9] S. Sidiropoulos and M. Horowitz. “ A Semi-Digital Dual Delay-Locked Loop,” IEEE Journal of Solid-state Circuits, vol. 32, pp. 1683-1692, Nov. 1997.
[10] Y. Jung, S. Lee, D. Shim, W. Kim, C. Kim, and S. Cho, “ A Dual-Loop Delay-Locked Loop using Multiple Voltage-Controlled Delay Lines,” IEEE Journal on Solid-state Circuits, vol. 36, no. 5, pp. 784-791, May 2001.
[11] S. Tanoi, T. Tanabe, K. Takahashi, S. Miyamoto and M. Uesugi, “ A 250-622MHz Deskew and Jitter-Suppressed Clock Buffer Using Two-Loop Architecture”, IEEE Journal of Solid-State Circuits, vol.31, no.4, pp. 487-493, Apr. 1996.
[12] Yong-Bin Kim and Tom Chen, “A CMOS Delayed Locked Loop (DLL) For Reducing Clock Skew to Under 500ps”, IEEE, pp.681-682, 1997.
[13] C.-K. Liang, R.-J. Yang, and S.-I. Liu, “An All-Digital Fast-Locking Programmable DLL-Based Clock Generator,” IEEE Transactions on Circuit and Systems,, vol. 55, no. 1, pp. 361-369,Feb. 2008.
[14] J.-H. Kim, Y.-H. Kwak, M. Kim, S.-W. Kim, and C. Kim, “A 120-MHz 1.8-GHz CMOS DLL-Based Clock Generator for Dynamic Frequency Scaling,” IEEE Journal of Solid-State Circuits, vol. 41, no. 9, pp. 2077-2082, Sep. 2006.
[15] C.-C. Chung and C.-Y. Lee, “A New DLL-Based Approach for All-Digital Multiphase Clock Generation,” IEEE Journal of Solid-State Circuits, vol. 39, no. 3, pp. 469-475, Mar. 2004.
[16] C. Kim, I.-C. Hwang, and S.-M. Kang, “Low-Power Small-Area ±7.28-ps-jitter 1-GHz DLL-Based Clock Generator,” IEEE Journal of Solid-State Circuits, vol. 37, no. 11, Nov. 2002.
[17] J. Christiansen, “An Integrated High Resolution CMOS Timing Generator Based on An Array of Delay Locked Loops”, IEEE Journal of Solid-State Circuits, vol. 31, pp. 952-957, July 1996.
[18] H.-H. Chang, R.-J. Yang, and S.-I. Liu, “Low Jitter and Multirate Clock and Data Recovery Circuit Using a MSADLL for Chip-to-Chip Interconnection,” IEEE Trans. Circuits and Systems-I: Regular Papers, vol. 51, pp. 2356-2364, Dec. 2004.
[19] X. Maillard, F. Devisch, and M. Kuijk, “A 900-Mb/s CMOS Data Recovery DLL Using Half-Frequency Clock,” IEEE Journal of Solid-State Circuits, vol. 37, pp. 711-715, Jun. 2002.
[20] T.-H. Lee, and J.-F. Bulzacchelli, “ A 155-MHz Clock Recovery Delay- and Phase-Locked Loop," IEEE Journal of Solid-State Circuits, vol. SC-27, no. 12, pp. 1736-1746, Dec. 1992.
[21] K.-H. Cheng, S.-M. Chang, S.-Y. Jiang, and W.-B. Yang, “A 2GHz Fully Differential DLL-Based Frequency Multiplier for High Speed Serial Link Circuit,” IEEE International Symposium on Circuits and Systems, vol.2, pp. 1174-1177, May. 2005.
[22] G. Chien, “Low-Noise Local Oscillator Design Techniques Using a DLL-Based Frequency Multiplier for Wireless Applications,” Ph.D. dissertation, Univ. of California, Berkeley, 2000.
[23] T. Kirihata et al., ”A 113mm2 600Mb/s/pin 512Mb DDR2 SDRAM with Vertically-Folded Bitline Architecture,” IEEE ISSCC Digest of Technical Papers, pp. 382-383, Feb., 2001.
[24] J. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques”, IEEE Journal of Solid-State Circuits, vol. 31, no. 11, Nov. 1996.
[25] 王志傭, “應用於高速數位系統之時脈同步電路的設計與製作”, 國立台灣大學電機工程研究所碩士論文,民國八十七年六月.
[26] J. Park, Y. Koo, and W. Kim, “A Semi-Digital Delay Locked Loop for Clock Skew Minimization”, IEEE Symposium on VLSI Design, pp. 584-588, Jan. 1999.
[27] W. Rhee, “ Design of High-Performance CMOS Charge Pumps in Phase Locked Loops,” IEEE Int. Symp. Circuits and Systems, pp. 545-548, 1999.
[28] 劉深淵, 楊清淵 “鎖相迴路”, Nov. 2006.
[29] G. Wegmann, E. Vittoz, and F. Rahali, “ Charge Injection in Analog MOS Switches,” IEEE Journal of Solid-State Circuits, vol. SC-22, pp. 1091-1097, Dec. 1987.
[30] F. Yuan, M. Youssef, and Y. Sun, “Efficient Modeling and Analysis of Clock Feed-through and Charge Injection of Switched-current Circuits,” CCECE’01, vol. 1, Toronto, ON, Canada, pp. 573-578, May 2001.
[31] B. Razavi, “Design of Analog CMOS Integrated Circuit”, McGraw-Hill, 2001.
[32] H. Sutoh, K. Yamakoshi, and M. Ino, “Circuit Technique for Skew-Free Clock Distribution,” in IEEE Custom Integrated Circuits Conf., pp. 163-166, 1995.
[33] C.-S. Hwang, W.-C. Chung, C.-Y. Wang, H.-W. Tsao, and S.-I. Liu,“ A 2V Clock Synchronizer Using Digital Delay-Locked Loop,” Proc. APASIC, 91-94, 2000.
[34] R.-J. Yang and S.-I. Liu, “A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm,” IEEE Journal of Solid-State Circuits, vol. 42, no. 2, pp. 361-373, Feb. 2007.
[35] G.-K. Dehng, J.-W. Lin, and S.-I. Liu, “A Fast-Lock Mixed-Mode DLL Using a 2-b SAR Algorithm,” IEEE Journal of Solid-State Circuits, vol. 36, no. 10, pp. 1464-1471, Oct. 2001.
[36] 闕壯穎, “二進位搜尋延遲鎖定迴路,” 國立台灣大學電機工程研究所碩士論文,民國九十年六月.
[37] J.-R. Yuan, and C. Svensson, “Fast CMOS Nonbinary and Counter”, Electron Lett., vol. 29, pp. 1222-1223, June 1993.
[38] T. Okayasu et al., “1.83ps-Resolution CMOS Dynamic Arbitrary Timing Generator for >4GHz ATE Applications,” IEEE ISSCC Dig. Tech. Papers, pp.522-523, February 2006.
[39] W. S. T. Yan and H. C. Luong, “A 900-MHz CMOS Low-Phase-Noise Voltage-Controlled Ring Oscillator,” IEEE Trans. Circuits and System II, vol. 48, pp. 216-221, Feb. 2001.
[40] H-H Chang, J-Y Chang, C-Y Kuo, and S.-I. Liu, “A 0.7-2GHz Self-Calibration Multiphase Delay-Locked Loop,” IEEE Journal of Solid-State Circuits, vol. 41, no. 5, pp.1051-1061, May 2006.
[41] H-Y Wu, “ Design and Application of CMOS DLL in Delay Generator and PWCL,” Graduate Institute of Electronics Engineering College of Electrical Engineering & Computer Science National Taiwan University, Oct 2007.
[42] A. Rossi, and G. Fucili, “Nonredundant Successive Approximation Register for A/D Converters,” IEEE Electronics Letters, vol. 32, no. 12, pp. 1055-1057, June 1996.
[43] S.-J. Bae, H.-J. Chi, Y.-S. Sohn, and H.-J. Park, “A VCDL-Based 60-760-MHz Dual-Loop DLL with Infinite Phase-Shift Capability and Adaptive-Bandwidth Scheme,” IEEE Journal of Solid-State Circuits, vol. 40, no. 5, pp. 1119-1129, May 2005.
[44] H.-H. Chang and S.-I. Liu, “A Wide-range and Fast-Locking All-Digital Cycle-Controlled Delay-Locked Loop,” IEEE Journal of Solid-State Circuits, vol. 40, no. 3, pp. 661-670, Mar. 2005.
[45] B.-G. Kim and L.-S. Kim, “A 250MHz-2GHz Wide-Range Delay-Locked Loop,” IEEE Journal of Solid-State Circuits, vol. 40, no. 6, pp. 1310-1321, Jun. 2005.