數位至時間轉換器被廣泛應用在自動測試儀器中，由於現今積體電路系統發展迅速，對各種高解析度之轉換器需求也急速增加，因此，高精度數位至時間轉換器的地位也日漸重要，為此，本論文提出利用兩組延遲鎖定迴路(Delay Locked Loop、簡稱DLL)為核心來實現高精度數位至時間轉換器，且利用循序漸近暫存器(Successive-Approximation Register、簡稱SAR)來取代傳統式延遲鎖定迴路中的充電幫浦與迴路濾波器，其目的是為了抑制充電幫浦的充放電流不匹配與切換時間誤差所產生的抖動，此架構同時也省略了迴路濾波器，因此，不僅可達到低抖動(Jitter)，亦可減少晶片面積，降低成本。本電路所使用的製程為TSMC 1P6M 0.18 μm，操作頻率在420 MHz時，解析度為10 ps，最大脈衝寬度可達1.2 μs以上，總功率消耗為28.3 mW，主要晶片面積為0.33 mm2。

Digital to time converter (DTC) is widely used in automatic testing instruments. The needs of high resolution converter are increasing rapidly due to the speed of VLSI development nowadays. Therefore, DTC is getting more and more important. This thesis proposes a high accuracy DTC with dual delay locked loop (DLL). For the purpose of reducing the jitter from the current mismatch and switching time errors, the proposed DLL is used to replace the traditional charge pump and loop filter by successive-approximation register (SAR). Therefore, the proposed DTC can not only achieve low jitter but also reduce chip area for reducing the cost. The proposed DTC is produced by TSMC 1P6M 0.18 μm process. The resolution of the proposed DTC is up to 10ps. The maximum measurement range is 1.2 μs operating at 420 MHz. The power consumption is 28.3 mW. The die size is 0.33 mm2.

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