在SoC (System on Chip) 功能越來越多元、越複雜的時代，造成資料的存取越龐大，因此如何提升記憶體的存取速度是一個重要的問題。雖然記憶體的時脈不斷的提升，但其存取速度卻依然遠低於處理器速度。因此，若要增加SoC 的效能，就需改善記憶體存取的速度。為此，設計一個能有效率的記憶體控制器顯得相當重要。
ARM Cortex系列的微控制器廣大應用於SoC晶片中，所以本論文設計了一個符合AMBA系列中AXI4介面及符合SDRAM DDR4介面的SDRAM控制器。此SDRAM控制器分為四個區塊，分別為非同步接收AXI4指令區塊、指令排程區塊、記憶體物理層區塊、記憶體資料回傳區塊。利用AXI的隨意傳輸與爆發模式傳輸型態，優先規劃好存取流程，結合DDR4 bank groups的區塊特性，可有效地減少存取時所需的等待時間，因而提升記憶體的存取效能。
完成的記憶體控制器符合DDR4 SDRAM與AMBA系列AXI4規範，可以依照不同的存取情況，做出最有效率的存取流程。在Xillinx ISE Virtex6上進行合成與模擬，一共使用了643個邏輯閘與813個暫存器，以及465個LUT做為記憶體，倍頻後最高頻率為245.28 MHz。

In the era of more and more complex functions in SoC (System on Chip), the access to data is so huge that how to improve the access speed of the memory is an important issue. Although the clock of memory continues to increase, its access speed is still much lower than the processor speed. Therefore, to increase the performance of the SoC, it is necessary to improve the performance of memory access. For this reason, it is important to design an efficient memory controller.
The ARM Cortex series of microcontrollers are widely used in SoC chips, so this thesis designed an SDRAM controller that conforms to the AXI4 interface in the AMBA series and conforms to the SDRAM DDR4 interface. The SDRAM controller is divided into four blocks, which are asynchronous receiving AXI4 instruction block, instruction scheduling block, memory physical layer block, and memory data return block. By exploiting the properties of the burst type transmission and AXI random transmission, combined with the characteristics of the DDR4 bank groups and proper priority scheduling, can effectively reduce the waiting time required for access, thereby improving the memory access performance.
The completed memory controller conforms to the DDR4 SDRAM and AMBA series AXI4 specifications and can make the most efficient access process according to different access conditions. Synthesis and simulation are performed on the Xilinx ISE Virtex6. A total of 643 logic gates and 813 registers are used, and 465 LUTs are used as the memory. The highest frequency after frequency multiplication was 245.28 MHz.

[1] ARM, ARM® AXI and ACE Protocol Specification-AXI3, AXI4, AXI5, ACE andACE5, 2017.

[2] Micron, DDR4 SDRAM MT40A1G4 MT40A512M8 MT40A256M16, 2014.

[3] ARM, ARM® Cortex®-A72 MPCore Processor Technical Reference Manual, 2016.

[4] ARM, ARM® Cortex®-A9 Technical Reference Manual, 2016.

[5] ARM, AXI Interconnect v2.1 LogiCORE IP Product Guide Vivado Design Suite, 2016.

[6] ARM, ARM® Cortex®-A Series Technical Reference Manual, 2015.

[7] Amit Bakshi, and Sudhanshu Shekhar Pandey, “ASIC Implementation of DDR SDRAM Memory Controller,＂IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology, pp. 74-78, Mar. 25, 2013.

[8] Haytham Ashour, “Design, Simulation and Realization of a Parametrizable, Configurable and Modular Asynchronous FIFO,＂Science and Information Conference, pp.1391-1395, Jul. 28, 2015.

[9] Md. Ashraful Islam, Md. Yeasin Arafath, and Md. Jahid Hasan, “Design of DDR4 SDRAM Controller,＂The 8th International Conference on Electrical and Computer Engineering, pp. 148-151, Dec. 20, 2014.

[10] Pooran Singh, Bhupendra Reniwal, Vikas Vijayvargiya, and Santosh Kumar Vishvakarma, “Design of high speed DDR SDRAM controller with
less logic utilization,＂The 2nd International Conference on Devices, Circuits and Systems, pp. 1-6, Mar. 6, 2014.

[11] 黃文詮, AMBA 相容之動態記憶體控制器智財設計與驗證, 國立台灣科技大學電子工程系碩士學位論文, 11/17, 2009

[12] 張耿華, 設計與實現一個基於AXI4介面的DDR4-SDRAM控制器, 國立台灣科技大學電子工程系碩士學位論文, 05/10, 2018

[13] 鄭宇良, 設計與實現一個符合AHB5介面的DDR4-SDRAM控制器, 國立台灣科技大學電子工程系碩士學位論文, 06/06, 2018

[14] 洪銘冠, 設計與實現一個AXI4介面相容的DDR4-SDRAM控制器, 國立台灣科技大學電子工程系碩士學位論文, 01/30, 2019