簡易檢索 / 詳目顯示
| 研究生： |
陳柏宇 Po-yu Chen |
|---|---|
| 論文名稱： |
以FPGA實現之高精度游標卡尺法數位至時間轉換電路 A Field-Programmable Gate Array based High Accuracy Vernier Digital-to-Time Converter |
| 指導教授： |
陳伯奇
Poki Chen |
| 口試委員: |
劉深淵
Shen-Iuan Liu 鄒應嶼 Ying-Yu Tzou 王朝欽 Chua-Chin Wang 姚嘉瑜 Chia-Yu Yao |
| 學位類別： |
碩士 Master |
| 系所名稱： |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
| 論文出版年： | 2009 |
| 畢業學年度： | 97 |
| 語文別： | 中文 |
| 論文頁數： | 97 |
| 中文關鍵詞： | 數位至時間轉換電路 、自動測試設備 、場可程式規劃之邏輯閘陣列 、數位脈衝產生器 、游標卡尺 、高精度 |
| 外文關鍵詞： | DTC, ATE, FPGA, Digital Pulse Generator, Vernier, High-accuracy |
| 相關次數： | 點閱：407 下載：11 |
| 分享至: |
| 查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
在一切講求效率的時代，驅使產業界漸次朝向全面自動化發展，讓自動化測試設備(Automatic Test Equipment、簡稱ATE)的運用更為廣泛。相較於人工或半自動化測試，自動化測試設備能快速偵測產品優劣，尤其對高科技領域更為有利，不但可以加速測試速度，同時又可將人為的錯誤降到最低。其中，更可將測試系統全部內建到電路中，稱之為內建自我測試(Built-In Self Test、簡稱BIST)，可以大幅簡化外部測試設備、降低測試所花費的代價。
數位信號輸入前端模組乃是自動化測試設備最廣為應用的模組之一，該模組的主要電路是由數位至時間轉換電路(Digital-to-Time Converter、簡稱DTC)組成，經由數位控制字組(Digital Control Words)，來控制一連串延遲線，並對輸入信號產生適當時間延遲，形成控制信號。將所需要的控制信號透過測試通道將控制信號傳送至待測物(Device Under Test、簡稱DUT)，以測試待測物的反應，再與內部記憶體所預存結果相比較，用來斷定待測物的輸出與期望結果是否相符合，並得知待測物是否能在額定的時序規格內正常工作。
有鑒於全客製化的研發過程相當耗時、耗費，對於發展雛型(Prototype)上造成不小的限制，為了減少研發時間、降低研發成本，本論文運用數位電路設計的角度來取代並簡化純類比電路的功能，基於游標卡尺法(Vernier)的設計原則以及相對時間延遲的手法，打破過去其他文獻以純類比實現數位至時間轉換電路的觀念，並以全數位介面的場可程式規劃之邏輯閘陣列(Field Programmable Gate Array、簡稱FPGA)平台創新開發「游標卡尺法之高精度數位至時間轉換電路」。有效解析為兩組鎖相迴路輸出週期之差值，以ALTERA公司之Stratix III FPGA晶片來實現，有效解析度可達1.58微微秒，對應之差分與整體非線性誤差只有-0.086~+0.12 LSB與-0.95~+0.75 LSB而已。在51個有效輸入位元的運作下，可操作範圍達到59.29分鐘的歷史紀錄。該FPGA可同時實現224組數位至時間轉換器，平均每個通道只需422個邏輯單元與84組暫存器而已，每個通道平均僅消耗3.3057毫瓦。同時，在0℃~85℃溫度範圍內有效解析度的變異量也只有-0.049~0.034微微秒，成效卓著。
Nowadays, automatic test equipments (ATE) are widely adopted in the industry to increase the fabrication efficiency. Compared with manually or semi-automatic testing equipments, ATE provides not only fast defect detection, higher operation speed but also less human-made errors. Specially, it benefits the high-tech industries facing strong competitions more than ever. For further cost reduction and external instrumentation equipment simplification, built-in self-test (BIST) becomes the main stream of both academic research and industrial application for ATE.
The digital-to-time converter (or digital pulse generator), one of the most important front end cores of digital ATE, converts the digital input to a corresponding time signal with a width proportional to the input for DUT testing and is extensively adopted by digital IC BIST circuits.
Based on vernier principle and relative time generation, the effective resolution is made equivalent to the period difference of two phase-locked loops. Realized by ALTERA Stratix III FPGA, the finest DTC resolution of 1.58 ps is achieved. The DNL and INL are verified to be -0.086~+0.12 LSB and -0.95~+0.75 LSB respectively for input value carried from 1 to 1026. The widest operation range of 59.29 minutes is accomplished with 51 functioning input bits. Except for two shared PLLs, there are only 422 combinational ALUTs and 84 dedicated logic registers utilized per channel for 224-channel circuit implementation. The power consumption per channel is simulated to be 3.3057 mW only. Meanwhile, to demonstrate the stability of the DTC against temperature variation, the measurement was done for every 20℃ to cover the temperature operation range, 0℃~85℃, of the FPGA chip in a Programmable Temperature & Humidity Chamber. The effective resolution only deviates -0.049~0.034 ps over the temperature operation range of the FPGA chip.
[1] J. A. Gasbarro and M. A. Horowitz, “Integrated Pin Electionics for VLSI Functional Testers,” IEEE J. Solid-State Circuits, Vol.24, No.2, pp. 331~337, Apr. 1989.
[2] J. Chapman, J. Currin and S. Payne, “A Low-Cost High-Performance CMOS Timing Vernier for ATE,” IEEE ITC, pp. 459-468, Oct. 1995.
[3] J. Chapman, “High-Performance CMOS-Based VLSI Testers:Timing Control and Compensation,” IEEE ITC, pp. 59-67, Sept. 1992.
[4] Robbins et al., “Low cost timing generator for automatic test equipment operating at high data rates,” U.S. Patent, No.5566188, Oct. 15, 1996.
[5] S. Katsu, T. Ueda, M. Kazumura and G. Kano, “A GaAs Programmable Timer with 125ps Delay-Time Resolution,” IEEE ISSCC, pp. 16~17, Feb. 1988.
[6] AD9501 digitally programmable delay generator, available from the Analog Devices, Inc., www.analog.com.
[7] T.-I. Otsuji and N. Narumi, “A 10-ps resolution , process-Insensitive timing generator IC,” IEEE J. Solid-State Circuits, Vol.24, No.5, pp. 1412-1417, OCT. 1989.
[8] T.-I Otsuji and N. Narumi, “A 3-ns range, 8-ps resolution, timing generator LSI utilizing Si bipolar gate array,” IEEE J. Solid-State Circuits, Vol.26, pp. 806-811, May 1991.
[9] C.-W. Branson, “Integrated Pin Electronics for a VLSI test system,” IEEE Transaction on Industrial Electronics, Vol.36, pp. 23-27, May 1989.
[10] Motorola, Inc., “MC10E195,” Motorola semiconductor technical data, available from the ON Semiconductor Inc., www.onsemi.com.
[11] J. Christiansen, “An integrated high resolution CMOS timing generator based on an array of delay locked loops,” IEEE J. Solid-State Circuits, Vol.31, pp. 952-957, July 1996.
[12] F. Baronti, L. Fanucci, D. Lunardini, R. Roncella and R. Saletti, “A High-Resolution DLL-Based Digital-to-Time Converter for DDS Applications,” IEEE International Frequency Control Symposium and PDA Exhibition, pp. 649-653, May 2002.
[13] T.-I. Otsuji, “A picosecond-Accuracy, 700-MHz Range, Si-Bipolar Time Interval Counter LSI,” IEEE J. Solid-State Circuits, Vol.28, pp. 941-947, Sept. 1993.
[14] T.E. Rahkonen, J.T. Kostamovaara, “The Use of Stabilized CMOS Delay Line for the Digitization of Short Time Intervals,” IEEE J. Solid-State Circuits, Vol.28, pp. 887-894, Aug. 1993.
[15] A. Hajimiri, S. Limotyrakis and T.H. Lee, “Jitter and Phase Noise in Ring Oscillators,” IEEE J. Solid-State Circuits, Vol.34, No.6, pp. 790-804, June 1999
[16] P. Chen, C.-C. Chen, J.-C. Zheng and Y.-S. Shen, “A PVT Insensitive Vernier-Based Time-to-Digital Converter with Extended Input Range and High Accuracy,” IEEE Trans. on Nuclear Science, Vol.54, pp. 294-302, Apr. 2007.
[17] T.-Y. Wang, S.-M. Lin and H.-W. Tsao, “Multiple Channel Programmable Timing Generators With Single Cyclic Delay Line,” IEEE Trans. Instrum. Meas., Vol.53, pp. 1295-1303, Aug. 2004.
[18] B. Arkin, “Realizing a Production ATE Custom Processor and Timing IC Containing 400 Independent Low-Power and High- Linearity Timing Verniers,” IEEE ISSCC, pp.348-349, Feb 2004
[19] N. Weste and K. Eshraghian, “Principles of CMOS VLSI design,” Addison Wesley Longman, 2nd Edition, 1994.
[20] M. Suda, K. Yamamoto, T. Okayasu, S. Kantake, S. Sudou and D. Watanabe, “CMOS High-Speed, High-Precision Timing Generator for 4.266-Gbps Memory Test System,” IEEE ITC, pp. -866, Nov. 2005.
[21] T. Okayasu, M. Suda, K. Yamamoto, S. Kantake, S. Sudou and D. Watanabe, “1.83ps-Resolution CMOS Dynamic Arbitrary Timing Generator for >4GHz ATE Applications,” IEEE ISSCC, pp. 2122- 2131, Feb. 2006.
[22] Verilog FPGA晶片設計, 林灶生, 劉紹漢編著
[23] J. Wu, Z. Shi and I. Y. Wang, “Firmware-only Implementation of Time-to-Digital Converter (TDC) in Field-Programmable Gate Array (FPGA),” IEEE Nuclear Science Symposium Conference Record, Vol.1, pp. 19-25, Oct. 2003.
[24] J. Song, Q. An and S. Liu, “A High-Resolution Time-to-Digital converter Inplemented in Field-Programmable-Gate-Arrays,” IEEE Transactions on Nuclear Science, Vol.53, No.1, pp. 236-241, Feb. 2006.
[25] H. Zhang, X. Li and Y. Bian, “High-Resolution and Multi-Channel Time Interval Counter Using Time-to-Digital Converter and FPGA,” IEEE International Frequency Control Symposium, pp. 1324-1326, June 2007.
[26] P. Chen, M.-C. Shie, Z.-Y. Zheng, Z.-F. Zheng and C.-Y. Chu, “A Fully Digital Time Domain Smart Temperature Sensor Realized with 140 FPGA Logic Elements,” IEEE Transactions on Circuits and Systems I, Vol.54, pp. 2661-2668, Dec. 2007.
[27] “ML505 and ML506 Evalution Platform: User Guide,” available from the Xilinx Corporation, www.xilinx.com.
[28] “Stratix II GX EPS2GX90 Transceiver Signal Integrity Development Board: Reference Manual,” available from the Altera Corporation, www.altera.com.
[29] “Datasheet: ALTERA DE3 Development and Education Board User Manual,” available from the Terasic Technologies Inc., www.terasic.com.
[30] “Virtex-5 FPGA datasheet: DC and Switching Characteristics,” available from the Xilinx Corporation, www.xilinx.com.
[31] “PLLs in Stratix II and Stratix II GX,” available from the Altera Corporation, www.altera.com.
[32] “Stratix II GX Device Handbook: DC and Switching Characteristics,” available from the Altera Corporation, www.altera.com.
[33] “Clock Networks and PLLs in Stratix III Devices,” available from the Altera Corporation, www.altera.com.
[34] “Stratix III Device Datasheet: DC and Switching Characteristics,” available from the Altera Corporation, www.altera.com.
[35] “Datasheet: Synthesized Clock Generator CG635-DC to 2.05 GHz low-jitter clock generator,” available from the Standard Research System Inc., www.thinkSRS.com.
[36] “Datasheet: Digital Phosphor Oscilloscopes and Digital Serial Analyzers,” available from the Agilent Corporation, www.agilent.com.
[37] 81110A 165/330MHz Pulse/Data Generator, available from the Agilent Corporation, www.agilent.com.
