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研究生： 溫俊彥
Jyun-Yan Wun
論文名稱： 使用MEMS電感之壓控振盪器及注入鎖定除頻器之設計
Design of Voltage-Controlled-Oscillators Using MEMS Inductor and Injection-Locked Frequency Dividers
指導教授： 莊敏宏
Miin-Horng Juang
張勝良
Sheng-Lyang Jang
口試委員: 徐敬文
Ching-Wen Hsue
徐世祥
S. H. Hsu
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2009
畢業學年度： 97
語文別： 英文
論文頁數： 104
中文關鍵詞： 壓控振盪器 、注入鎖定除頻器 、四相位注入鎖定除頻器
外文關鍵詞： BiCMOS, QILFD
相關次數： 點閱：249  下載：2 
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    • 此論文提出了一個壓控振盪器(VCO)及二個注入鎖定除頻(ILFDs)，它們分別使用了標準台積電0.18微米CMOS製程、CIC MEMS後製程和0.35微米SiGe BiCMOS製程去實現。

    首先是設計一個5 GHz全NMOS考畢子壓控振盪器使用TSMC 0.18μm CMOS 1P6M製程。共振腔之電感是使用CIC MEMS製程來製作。在供應電壓為1.2V下，振盪頻率為4.76 GHz，相位雜訊在1 MHz的偏移頻率下為-119.33 dBc/Hz，FOM為-187.46 dBc/Hz。本VCO之總消耗功率為3.48 mW。可調電壓由0V至1.8V，可調範圍從4.76 GHz至5.09 GHz約為0.33 GHz。

    其次是一個LC-tank注入鎖定除頻器(ILFD)，此ILFDs有一個直接注入MOSFET和一個尾端注入的HBT，採用0.35-µm SiGe 3P3M BiCMOS CMOS製程，這個除四功能的完成是從尾端注入雙即興電晶體的基極端。量測結果電壓可調範圍為0V~1.8V，且頻率可調範圍為2.12-GHz~2.76-GHz，在注入功率0 dBm時，除2(除4)之操作頻率範圍為4.2~6.7(9.0~12.03)GHz。供應電壓Vdd=1.1 V，其消耗功率為2.6 mW。

    最後本論文提出一個雙共振腔的四相位注入鎖定除頻器。此雙共振腔的特性被延伸使用於操作範圍。QILFD是由兩個使用電感耦合的差動的壓控振盪器和兩個NMOS開關所組成，此開關與QVCO之共振腔並聯且為提供注入訊號所使用。此CMOS ILFD 是使用TSMC 0.18μm CMOS 1P6M製程，且核心電路於供應電壓為0.75 V之消耗功率為3.4 mW。在注入功率0 dBm時，除2之操作頻率範圍為6.3~10.3GHz。

    This thesis presents one voltage controlled oscillator and two injection locked frequency dividers. which are implemented by using standard TSMC 0.18um CMOS process, CIC micro-electromechanical systems (MEMS) post-process and SiGe 0.35um BiCMOS process respectively.

    Firstly, a 5GHz all-nMOS Colpitts voltage-controlled oscillator (VCO) is designed and implemented inresonator was fabricated with the Chip Implementation Center (CIC) micro-electromechanical systems (MEMS) process. At the supply voltage of 1.2 V, the output phase noise of the VCO is -119.33 dBc/Hz at 1MHz offset frequency from the carrier frequency of 4.76 GHz, and the figure of merit is -187.46 dBc/Hz. Total VCO core power consumption is 3.48 mW. Tuning range is about 0.33 GHz, from 4.76 to 5.09 GHz, while the control voltage was tuned from 0 V to 1.8 V.

    An LC-tank injection locked frequency divider (ILFD) is proposed, and the ILFDs with a direct-injection MOSFET and a tail-injection HBT were implemented in the TSMC 0.35μm SiGe 3P3M BiCMOS technology. Measurement results show that when the tuning voltage is tuned from 0 V to 1.8 V, the free-running oscillation frequency of ILFD is tunable from 2.29 GHz to 2.94 GHz, and at the incident power of 0 dBm the divide-by-2/(-4) operation range is from the incident frequency 4.2 to 6.7/(9.0 to 12.03) GHz. The core power consumption is 2.6 mW at Vdd=1.1 V.

    Finally, this thesis presents a divide-by-2 quadrature injection-locked frequency divider (QILFD) with dual resonance resonator. The dual resonance property is used to extend the operation range. The QILFD consists of two differential voltage controlled oscillators coupled with transformers and two NMOS switches, which are in parallel with the QVCO resonators for signal injection. The proposed CMOS ILFD has been implemented with the TSMC 0.18-μm CMOS technology and the core power consumption is 3.4mW at the supply voltage of 0.75 V. At the input power of 0dBm, the total divide-by-2 operation range is from 6.3 GHz to 10.3 GHz. The phase noise of the locked output spectrum is lower than that of free running ILFD in the 2 mode. The phase deviation of quadrature output is about 0.51.

    中文摘要 I Abstract III 誌謝 V CONTENTS VI LIST OF FIGURES VIII CHAPTER 1 INTRODUCTION 1 1.1 BACKGROUND 1 1.2 PLL ARCHITECTURE 2 1.3 OVERVIEW OF THIS THESIS 4 CHAPTER 2 THE THEORY OF OSCILLATORS 5 2.1 BASIC THEORY OF OSCILLATORS 5 2.1.1 TWO-PORT (FEEDBACK) VIEW 5 2.1.2 ONE-PORT (NEGATIVE RESISTANCE) VIEW 7 2.2 QUALITY FACTOR (Q) 9 2.3 PHASE NOISE (PN) 12 2.4 CAPACITOR AND VARACTOR 17 2.4.1 CAPACITOR 17 2.4.2 VARACTORS 19 2.4.2.1 THE INVERSION-MODE MOS CAPACITOR 22 2.4.2.2 THE ACCUMULATION-MODE MOS CAPACITOR 24 2.4.2.3 SIMULATION OF VARACTOR 25 2.5 INDUCTOR AND TRANSFORMER 26 2.5.1 INDUCTOR 26 2.5.2 TRANSFORMER 35 2.6 OSCILLATOR AND PARAMETER OF VCO 40 2.6.1 CROSS COUPLE OSCILLATOR 40 2.6.2 PARAMETER OF VCO 41 2.7 THEORY OF INJECTION LOCKED FREQUENCY DIVIDER 45 2.7.1 INTRODUCTION 45 2.7.2 CLASSIFICATION OF ANALOG FREQUENCY DIVIDERS 45 2.7.3 CLASSIFICATION OF ILFDS 47 2.7.4 TOPOLOGY OF DIVIDE-BY-2 ILFD 50 CHAPTER 3 A LOW POWER ALL-NMOS COLPITTS VCO USING MEMS INDUCTOR 52 3.1 Introduction 52 3.2 Circuit Design of All-nMOS Colpitts VCO 53 3.3 Measurement and Discussion 55 3.4 Conclusion 60 CHAPTER 4 A LOW POWER LC-TANK SiGe BiCMOS INJECTION LOCKED FREQUENCY DIVIDER 62 4.1 Introduction 62 4.2 Circuit Design 63 4.3 Measurement and Discussion 65 4.4 Conclusion 71 CHAPTER 5 A LOW-POWER CMOS QUADRATURE INJECTION-LOCKED FREQUENCY DIVIDER WITH DUAL RESONANCE RESONATOR 72 5.1 Introduction 72 5.2 Design of QLFD 73 5.3 Measurement and Discussion 76 5.4 Conclusion 82 CHAPTER 6 CONCLUSIONS 83 REFERENCES 85

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