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研究生: 李國維
Kuo-wei Lee
論文名稱: 應用正交分頻多工電力線通信之智慧電錶系統
OFDM Power Line Communication forAutomatic Meter Management
指導教授: 柳宗禹
Tzong-Yeu Leou
口試委員: 賴坤財
Kuen-Tsair Lay
邱炳樟
Bin-Chang Chieu
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2010
畢業學年度: 98
語文別: 英文
論文頁數: 106
中文關鍵詞: 正交分頻多工電力線通信智慧電錶
外文關鍵詞: OFDM, PLC, Automatic Meter Management
相關次數: 點閱:246下載:2
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電力線遍佈世界上每個角落,除了使用電池的可攜裝置式只要需要使用電力的裝置幾乎都會連接上電力線。電力線網路可以說是全世界最大且隨手可及的網路界面。
這篇論文將依據PRIME 1.3 Draft 的 PHY Layer 的實體層架構規劃相關系統硬體實現,亦完成系統Matlab模擬並依據此調整硬體建構或系統線上調整時之系統參數。PRIME 的規格中包括了OFDM , 同步電路,資料編碼。雖然PRIME 這規格只是一個Draft ,但他卻是在電力線系統應用智能電表量測的全世界第一份標準規格。在這篇論文中,主要是針對 PRIME的規格作Matlab模擬,並且分析其相關系統特性並且在撰寫Matlab程式 同時也考慮到硬體的實踐。也因此我們整體系統是根據未來要可以硬體實踐為考量來設計,且必須同時考量將來系統的低成本設計的問題,提出一個經濟有效率的實踐方式。


The powerline network is the biggest network around the world. Most of the electric device will need to connect to the powerline while we using it, except the mobile device. The powerline is the existence of abundant pre-installed wires and wall outlets.

We will discuss the OFDM power line communication system base the define in PRIME 1.3 Draft PHY layer specification. In this thesis , we will build a matlab model to simulate the whole system operation, and use the simulation result as an reference when we build the hardware in the future. In the PRIME, it include the synchronization circuit ,data coding. Although the PRIME specification is only a draft version, it is the first one of the protocol specification of power line communication. We will been focus in building PRIME system in Matlab code, and considering the feasibility while we construct it.

摘要2 Abstract5 Table Content6 Chapter 1 Introduction8 Chapter 2 Power Line Channel Model12 2.1 Channel Noise12 2.2 Attenuation13 2.3 Multipath Effect15 2.4 Channel Model16 Chapter 3 System Configuration Based on PRIME19 3.1 Basic Principles of OFDM22 3.2 System Specification25 3.2.1 Scrambler26 3.2.2 Convolutional Encoder / Viterbi Decoder28 3.2.3 Interleaver38 3.2.4 OFDM Symbols42 3.2.5 Preamble43 3.2.6 Mapping and Demapping44 3.2.7 Pilot47 Chapter 4 Description of the implemented System48 4.1 System Specification48 4.2 Cyclic Prefix48 4.3 Symbol Timing Synchronization50 Chapter 5 Hardware Design and Implementation54 5.1 The Design Target54 5.2 The architecture of the FFT/IFFT56 5.3 Viterbi Decoder68 5.4 Maping & Soft Demaping74 5.5 Digital to Analog Converter Circuit77 5.6.Analog to Digital Converter Circuit78 5.7 Coupling circuit79 Chapter 6 Simulation Results80 Chapter 7 Conclusion86 Appendix A Matlab Code87 A.1 MAIN87 A.2 TX Matlab Code88 A.3 RX Matlab Code90 A.4 Damping Signal for Noise Generation91 A.5 TX FFT92 A.6 TX FFT92 A.7 PREAMBLE DETECTION93 A.8 VITERBI DECODER94 A.9 INTERLEAVING97 A.11 DEMAPPING98 Bibliography101

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