本論文設計實現一顆高精度十位元1GS/s電流導向式之數位至類比轉換器，在電流導向式的架構下有三種方式可供選擇，分別是單位電流源矩陣、二進位權重式和分段式架構，以往為了兼顧高速與高解析度的需求，通常會選擇分段式架構來實現，但分段式架構往往使得電路複雜度以及功耗大幅提升，為了在成本與性能之間做考量，本論文使用二進位權重式架構實現，探索二進位權重式架構的極限。傳統二進位權重式架構為了確保輸出電流的精準度，需以龐大的佈局陣列去匹配所有位元的電流源，佈局的複雜度以及面積隨之大幅拉升。因此本論文提出一種全新的複製-分割分流器架構，打斷位元間電流源的相依性，只需專注匹配每一位元的電流源，並藉由二階梯度消除(2nd Order Gradient Cancellation)佈局技巧，消除系統性不匹配的影響，以獲得高精度的輸出電流。
此數位至類比轉換器使用TSMC 90nm 1P9M製程實現，操作電壓為1.2V，量測結果顯示積分非線性誤差(INL)介於+0.48 LSB ~ -0.55 LSB，微分非線性誤差(DNL)介於+0.36 LSB ~ -0.45 LSB。在1GHz取樣頻率下，輸入頻率為1.22MHz時，無突波動態範圍(SFDR)達59.05dB，功率消耗為22mW，核心晶片面積為0.29 mm2。

A 10-bit 1GS/s current-steering digital-to-analog converter is proposed and implemented in this thesis. For current-steering DACs, there are three major architectures for implementation: Unary Current Source based, Binary-Weighted, and Segmented. Conventionally, segmented current-steering architecture was adopted for high accuracy DAC at the expense of complicated circuitry and high power consumption. For cost down and performance enhancement, this thesis adopts the binary-weighted architecture to explore the limits of this architecture. Accordingly, a current-splitter architecture along with the 2nd order gradient cancellation layout is utilized to ensure the required accuracy and ease circuit design.
The DAC is implemented in a TSMC 90 nm 1P9M CMOS technology and the operation voltage is 1.2V. The integral nonlinearity (INL) and differential nonlinearity (DNL) are measured to be +0.48 ~ -0.55 LSB and +0.36~-0.45 LSB respectively. The DAC achieves a maximum spurious free dynamic range (SFDR) of 59.05 dB for 1.22 MHz input frequency at 1GHz sampling rate. The power consumption is 22 mW and the active area is merely 0.29 mm2.

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