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研究生: 賴俊豪
Chun-Hao Lai
論文名稱: 正交分頻多工之天線模組設計
FPGA Design for OFDM Antenna Module
指導教授: 王煥宗
Huan-Chun Wang
口試委員: 林敬舜
Ching-Shun Lin
高典良
none
何政祐
none
葉濰銘
none
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2016
畢業學年度: 104
語文別: 中文
論文頁數: 64
中文關鍵詞: 嵌入式系統天線802.11FPGA
外文關鍵詞: Embedded system, RF, 802.11, FPGA
相關次數: 點閱:209下載:2
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隨著無線通訊與嵌入式系統的快速發展,本論文主要目標於天線模組之系統整合及應用,現今無線區域網路的使用頻段十分擁擠雜亂,為了迎接物聯網發展趨勢與避免資料傳輸時的碰撞,我們建立一個能夠支援多頻段的無線收發平台,基於802.11a/g 網路通訊協定,使用正交分頻多工技術建立無線收發的系統於實驗板上,使用2×2天線收發封包,依據不同調變方式測試其錯誤率、吞吐量、距離與通道情況,進而運用在無線區域網路之中,作為未來邁向物聯網的先決條件。將 AD-FMCOMMS3 RF天線配合 Virtex 6 FPGA 開發板,藉由 SoC( System On Chip ) 設計電路於晶片內部,再透過韌體控制其收發狀態,完成802.11通訊協定的傳輸模式,天線接收後經由自行設計的電壓控制電路、SPI控制電路、同步電路與傳輸介面來使其能夠正常解碼。嵌入式項目包含硬體與軟韌體設計,硬件系統是基於 Microblaze 處理器和 FPGA 的組合,而軟韌體則是賽靈思提供之軟體開發工具包(SDK)。


In recent years, wireless communication and embedded system develop rapidly. We are going to focus on antenna module integration and application in this paper. The use of wireless LAN band is so crowded and messy nowadays that we set up a platform which can transmit or receive in multiband. We use 2×2 MIMO OFDM to implement wireless LAN based on 802.11 a/g. According to different modulation mode, verify the bit error rate, throughput, distance and channel condition. We can apply on Internet of Things ( IoT ). AD-FMCOMMS3 combine with Virtex 6 FPGA WARP v3 and build embedded system in FPGA by System on Chip (SoC). Then use firmware to control the mode of transmission and reception. When antenna received the 802.11 packet, the signal pass through voltage gain amplifier, SPI control, clock synchronization and transmission interface. The embedded system included hardware / firmware design, hardware based on Microblaze processor and FPGA design. Firmware is developed on Xilinx SDK.

章節目錄 圖目錄 v 表目錄 vii 第一章 緒論 1 第二章 系統架構 3 2.1 正交分頻多工系統 3 2.1.1 OFDM的調變( Modulation ) 3 2.1.2 OFDM的正交性( Orthogonality ) 4 2.1.3 OFDM的解調變( Demodulation ) 5 2.1.4 OFDM調變/解調變的數位化 6 2.1.5 護衛區間(Guard interval)與循環字首( Cyclic Prefix ) 7 2.2 多輸入多輸出系統 8 2.3 傳送Tx / 接收Rx / MAC DCF 硬體架構 9 2.3.1 傳送端Tx 9 2.3.2 接收端Rx 11 2.3.3 MAC DCF硬體 13 2.4 802.11 架構 15 2.4.1 Distributed Coordination Function ( DCF ) 15 2.4.2 802.11無線網路訊框架構 17 第三章 實作平台 18 3.1 WARP v3 FPGA開發板 18 3.2 AD-FMCOMMS3-EBZ 開發板 19 3.3 模擬工具與平台 20 3.3.1 System Generator開發流程 22 3.3.2 建立IP方式 23 3.3.3 SDK 24 第四章 AD9361電路特性 26 4.1 傳送端訊號路徑 26 4.1.1 傳送端之數位訊號處理 26 4.1.2 傳送端之類比訊號處理 27 4.2 接收端訊號路徑 28 4.2.1 接收端之類比訊號處理 28 4.2.2 接收端之數位訊號處理 28 4.2.3 傳送端與接收端之數位訊號延遲 29 4.3 自動增益控制 30 4.3.1 Slow Attack AGC mode 30 4.3.2 Fast Attack AGC mode 31 第五章 嵌入式系統整合電路之實現 33 5.1 AD9361 與 Warp v3 之介面 33 5.1.1 AD9361 Intellectual Property ( IP ) 35 5.1.2 AD9361 User Constraint File ( UCF ) 36 5.2 Dual Clock First-In, First-Out ( FIFO ) RAM Buffer 38 5.3 AD9361與FIFO介面之時脈控制 41 5.4 AD9361 SPI 45 第六章 量測結果與頻譜分析 47 6.1 AD9361 測試訊號 47 6.2 802.11短封包( Null Data Transmit ) 49 6.3 802.11長封包( Hello World Transmit ) 51 6.4 Throughput結果比較 54 第七章 結論與未來展望 57 附錄: 附錄A AD9361_FMC_Schematics 58 附錄B LVDS Mode Data Path Signals 60 參考文獻 63

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