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研究生: 鍾墉
Yong Zhong
論文名稱: 階梯式灌孔感知的細節佈局
Via Ladder-aware Detailed Placement
指導教授: 方劭云
Shao-Yun Fang
口試委員: 呂學坤
Shyue-Kung Lu
李毅郎
Yih-Lang Li
劉一宇
Yi-Yu Liu
學位類別: 碩士
Master
系所名稱: 電資學院 - 電機工程系
Department of Electrical Engineering
論文出版年: 2019
畢業學年度: 107
語文別: 英文
論文頁數: 46
中文關鍵詞: 階梯式灌孔墩柱式灌孔細節佈局
外文關鍵詞: Via Ladder, Via Pillar, Detailed Placement
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隨著近代積體電路的製程不斷演進,導線的阻抗的影響以及其造成的訊號延遲的影響也顯著的提高。為了解決這個問題,一種新的灌孔構造──「階梯式灌孔」(Via Ladder)被提出。然而,在繞線階段前的階梯式灌孔擺置程序的低落成功率儼然成為了立即性的問題。在這篇論文中,我們透過實驗探討了階梯式灌孔擺置失敗的成因,並用嵌入到實際製程的標準元件庫(Standard Cell Library)的測資來驗證我們所觀察到的成因。實驗結果顯示階梯式灌孔擺置失敗的原因大致可以歸咎於以下:繞線軌道(Track)的對齊與否、其結構是否與電源電路交疊、其結構是否與其他階梯式灌孔交疊或超出邊界。為此,我們提出了一個細節佈局(Detailed Placement)流程,在流程當中考慮了所有需要擺置階梯式灌孔的標準元件,以期達到擺置成功率的最大化。在我們提出的演算法當中,我們首先為標準元件濾除掉了沒有達到擺置條件的位置,並且將所有需要擺置階梯式灌孔的標準元件移動到符合條件的位置。接下來,我們分別透過兩次的標準元件合法化機制(Legalization)來消除所有標準元件之間的重疊情形。該合法化機制是延伸自基於動態規劃的單行內細節佈局演算法。最後,我們透過標準元件的廣域移動來緩解太過擁擠導致合法化失敗的標準元件行。實驗結果顯示,在嵌入到實際製程的標準元件庫的測資當中,我們所提出的演算法可以達到平均97%的擺置成功率。


With the feature size shrinking down to 7 nm and beyond, the impact of wire resistance is significantly growing, and the circuit delay incurred by the metal wires is noticeable raising. To address this issue, a new technique called via ladder (or via pillar) insertion is presented. However, the poor success rate of via ladder insertion process before the routing stage immediately becomes a significant problem. In this thesis, we explore the causes of via ladder insertion failures by experiments on the benchmarks which are embedded in a real industrial cell library. The experiments show that the reasons for the low success rate may be attributed to the track alignment issue, power & ground stripe overlapping, and insufficient margin area. Therefore, we further propose a detailed placement flow which is aware of via ladder to maximize the success rate on via ladder insertion. In the proposed algorithm, we first filter out all of the infeasible solutions, and then move the via ladder-inserted cells to their eligible positions. Next, we adopted two-stage legalization method with high flexibility on cell order based on an extension to the dynamic programming-based detailed placement algorithm. Finally, we improve congested rows with a global movement process. Experiment results show that our algorithm increases the insertion rate by 54 to 58 percent, and achieves over 99% insertion rate in average on modified ISPD 2015 benchmarks.

Abstract List of Tables List of Figures Chapter 1. Introduction 1.1 Detailed Placement 1.2 Via Ladder 1.2.1 Track Alignment 1.2.2 Power/Ground Stripe Overlapping 1.2.3 Insucient Margin Area 1.3 Previous Work 1.4 Contributions 1.5 Thesis Organization Chapter 2. Via Ladder-aware Detailed Placement 2.1 Algorithm Flow 2.2 Eligible Row and Site Determination 2.3 Global Move for Eligible Row Assignment 2.4 Legalization 2.4.1 Legalization for V-cells 2.4.2 Legalization for N-cells 2.5 Global Move for Congested Row Improvement Chapter 3. Experimental Results 3.1 Environment and Benchmarks 3.2 Experiment Results Chapter 4. Conclusion Bibliography

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