在本論文中，我們設計了一個可配置性通用序列匯流排(Universal Serial Bus, USB)的功能核心智財(Intellectual Property, IP)。提供16組端點(endpoint)讓開發者設計USB周邊，其中端點0為控制傳輸(control transfer)端點，由內部使用。其餘端點1∼15可為中斷傳輸(interrupt transfer)、巨量傳輸(bulk transfer)或即時傳輸(isochronous transfer)，由開發者自行規劃使用。
本設計核心在實體層(physical layer)部份需搭配一個USB傳送接收器(transceiver)作為差分訊號轉換，使用的是Philips PDIUSBP11AD晶片。透過USB纜線可直接與電腦溝通，核心部份提供了循環冗餘核對(Cyclic Redundancy Check ,CRC)檢測、USB資料傳送狀態及端點選擇狀態…等訊息提示，節省開發USB周邊硬體、韌體及驅動程式的時間。
USB功能核心智財分別在Xilinx的Spartan-3 XC3S1500-4FG676 FPGA以及TSMC 0.35 μm元件庫(Cell Library)上完成實現與驗證。在FPGA設計部份，工作頻率為48 MHz，消耗了2875個LUT。在元件庫方面核心面積為1662.5 μm × 1831.2 μm，等效閘數(gate count) 為19216閘，在SS (Slow NMOS Slow PMOS model)模式下，平均消耗功率為44.92 mW。

In this thesis, we designed a configurable IP (Intellectual Property) of USB (Universal Serial Bus). The IP provides sixteen endpoints, numbered from 0 to 15, for designers to design their own customized USB devices. The endpoint 0 is reserved for the control transfer required by the IP itself. The rest of endpoints, i.e., endpoints 1 to 15, can be used for controlling interrupt transfer, bulk transfer, or isochronous transfer, and can be planned to use by the designers.
The designed core IP also includes the physical layer except the transceiver, which is implemented by using Philips PDIUSBP11AD chip. The entire design can then be communicated with PC (personal computer) through a USB cable and displays the message of CRC (Cyclic Redundancy Check) detected, status of USB data transfers, and endpoint selected. Hence, a lot of time may be saved when developing a USB device hardware, firmware, and driver.
The USB core IP has been implemented and verified with Xilinx Spartan-3 XC3S1500-4FG676 FPGA and TSMC 0.35 μm cell library. In the FPGA part, it operates at working frequency of 48 MHz and occupies 2875 LUTs. In the cell-based part, the core occupies 1662.5 μm × 1831.2 μm silicon areas, which is approximately equivalent to 19216 gates. The USB function core consumes about 44.92 mW in the SS (Slow NMOS Slow PMOS model) mode.

[1] http://www.usb.org/developers
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[3] Universal Serial Bus Specification, Revision 2.0, usb.org, 2000.
[4] Universal Serial Bus Specification, Revision 1.1, usb.org, 1998.
[5] Don Anderson, Universal Serial Bus System Architecture, Addison Wesley, 1998.
[6] Samir Palnitkar, Verilog HDL:A Guide to Digital Design and Synthesis, Prentice Hall, 1999.
[7] DATA SHEET of PDIUSBP11A Universal Serial Bus Transceiver, Philips Semiconductors, 2001.
[8] http://www.perisoft.net/bushound/index.htm
[9] USB Device Viewer, Copyright 1996-1998 Microsoft Corporation. http://www.beyondlogic.org/usb/usbdevdrvs.htm
[10] 林錫寬，快速上手USB單晶片，全華科技圖書股份有限公司，民93。
[11] 郭士秋，USB 2.0 理論與規範，儒林圖書有限公司，民94。