應用於無線多頻之連續時間三角積分類比數位轉換器晶片設計

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研究生：	黃琨傑 Kun-Jie Huang
論文名稱：	應用於無線多頻之連續時間三角積分類比數位轉換器晶片設計 The Continuous-Time Sigma-Delta ADC Chip Design for Wireless Broadband Applications
指導教授：	黃進芳 Jhin-Fang Huang 劉榮宜 Ron-Yi Liu
口試委員:	徐敬文 Ching-Wen Hsue 張勝良 Sheng-Lyang Jang 江正雄 Jen-Shiun Chiang
學位類別：	碩士 Master
系所名稱：	電資學院 - 電子工程系 Department of Electronic and Computer Engineering
論文出版年：	2012
畢業學年度：	100
語文別：	英文
論文頁數：	124
中文關鍵詞：	三角積分類比數位轉換器、抽樣濾波器、類比數位轉換器、正交帶通三角積分調變器
外文關鍵詞：	sigma-delta ADC, decimation filter, analog to digital converter, quadrature bandpass sigma delta modulator
相關次數：	點閱：264 下載：17
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在本論文中，包括有兩個連續時間三角積分調變器以TSMC 0.18 um 金氧半(CMOS)製程被設計與製作與一個抽樣濾波器(Decimation Filter)設計，第一個是應用於多頻帶的連續時間低通三角積分數位類比轉換器，其中三角積分調變器完成了晶片下線與量測結果，並結合抽取樣濾波器完成三角積分數位類比轉換器;此晶片採用了CICFF迴路濾波器，相較於傳統CIFF架構，其電容式前饋方式電路是一種簡單的實現方式且具有低功率消耗特性。此晶片時脈為160 MHz的情況下，在一個5MHz的頻寬內這個調變器量測到52 dB的動態範圍，SNDR為47.1 dB，IM3為-40.4 dB。在1.8 V的電源下量測的功率消耗是10.8 mW。包含Pads的晶片面積是1.09 (1.173 x 0.86) mm^2。
雖然三角積分數位類比轉換器能容忍類比電路的不完美特性，但其輸出需要經過抽取濾波器，此抽取濾波器由一個串聯積分梳狀濾波器(CIC Filter)及二個半帶濾波器(Halfband Filter)組成.超取樣三角積分調變器輸出訊號經由抽取濾波器降頻為奈奎斯特數位類比轉換器，此抽取樣濾波器有效將高頻雜訊濾除掉，同時也防止高頻雜訊折疊到低頻頻帶內，此連續時間低通三角積分數位類比轉換器後模擬結果為SNDR達到59.8 dB與63.5 dB動態範圍，功率消耗為79 mW.
此外，第二個調變器晶片為應用於LTE連續時間四相位帶通三角積分調變器，使用四相位帶通三角積分器可降低直流偏差(DC offset)與閃爍雜訊(Flicker Noise)。而為了移除一個被用在CIFF架構的加總放大器，電容式前饋架構同樣被使用，同時在迴路濾波器中加入了回授電阻去做最佳化零，此三角積分調變器採用一位元輸出以減少硬體的複雜性與功率消耗。此晶片在2.5 MHz的訊號頻寬內晶片量測到56 dB的動態範圍，SNDR為52.8 dB，功率消耗為18.5 mW。包含pad的總晶片面積為1.95 ( 1.3 x 1.5) mm^2。

In this thesis, two CT sigma-delta modulators are designed and fabricated. The first one is the continuous time lowpass ΣΔ ADC with one decimation filter for wireless broadband applications. In this chip, CICFF topology is applied. Compared with conventional CIFF topology, the capacitive feedforward architecture is a simple approach and has an advantage of low power dissipation.
For the first ΣΔ modulator, the modulator achieves a measured dynamic range of 52 dB over a 5 MHz signal bandwidth, SNDR of 47.1 dB, IM3 of -40.4 dB, power consumption of 10.8 mW at 1.8 V supply with 160 MHz clock frequency. Including pads, the overall chip area is 1.09 (1.173 x 0.86) mm^2. Although ΣΔ modulators have high tolerance for the imperfection of analog circuit, a decimation filtering the output stream of ΣΔ modulators enhance the ADC’s performance. The decimation filter consists of a cascaded integer and comb filter (CIC filter) and two halfband filters. The output signal of oversampling ΣΔmodulator is down converted by decimation filter; thus, a Nyquist rate bandwidth is obtained for the ΣΔ ADC. The decimation filter can filter noise from high frequency effectively and prevent high frequency noise from folding to desired baseband frequency range. The simulated results achieve SNDR of 59.8 dB, dynamic range of 63.5 dB, and power consumption of 79 mW.
The second modulator chip is the CT quadrature bandpass ΣΔ modulator for LTE application. Using the quadrature bandpass ΣΔ modulator can solve the problem of DC offset and flicker noise. Also, to erase the summation amplifier used in the CIFF topology, the capacitive feedforward structure is also employed. The loop filter is added the feedback resistor to optimize zero. The ΣΔ modulator adopt single bit which can reduce hardware complexity and power consumption. For the second ΣΔ modulator, the overall measured results achieve dynamic range of 56 dB over a 2.5 MHz input signal bandwidth, SNDR of 52.8 dB and power dissipation of 18.5 mW. The overall chip area is 1.95 (1.3 × 1.5) mm^2.

Chapter 1
Introduction      1
1 Motivation	1
2 Organization	2
Chapter 2 Basic Concepts of Delta Sigma Modulator  5
1 Introduction	5
2 Analog-to-Digital Conversion	5
3 Quantization	6
4 Performance Metrics	9
5 Sigma Delta Modulator	11
5. 1 Oversampling	11
5. 2 Noise-Shaping ΔΣ ADC	12
5. 3 Multi-Bit ΔΣ Modulator	13
5. 4 Dynamic Element Matching	13
5. 5 Continuous-Time and Discrete-Time Loop Filter	14
6 DT-to-CT Conversion of ΣΔ ADC	15
7 Frequency Compensation by the Feedforward or Feedback.	17
7. 1 Cascade of Integrators with Distributed Feedback (CIFB)	17
7. 2 Cascade of Integrators with Distributed Feedforward (CIFF)	18
8 Paper Survey	19
9 Summary	24
Chapter 3 The Continuous-Time Sigma-Delta Modulator Chip Design for LTE Application  25
1 Introduction	25
2 Design of the Continuous Time lowpass Delta Sigma ADC	26
2. 1 Specification	26
2. 2 Sigma-Delta ADC Circuit	26
2. 3 Loop Filter Design	27
2. 4 Zero Optimization and Root Locus	28
2. 5 Coefficients Design of Loop Filter	30
3 Effects of Non-Idealities on Lowpass ADC Performance.	31
3. 1 Finite Gain and Finite Bandwidth of Op Amp	31
3. 2 RC Product Variation	32
3. 3 Clock Jitter	33
3. 4 Excess Loop Delay	34
3. 5 DAC Element Mismatch	35
4 Circuit Implementation	35
4. 1 Op Amp Circuit	36
4. 2 Quantizer	38
4. 3 Current Steering DACs for Global Feedback	40
4. 4 Current Steering DACs for Local Feedback	41
4. 5 Data Weighted Averaging	41
5 Layout Consideration of Modulator	42
6 Simulation Results of Modulator	44
6. 1 Simulation of Output Swing of Op Amp	44
6. 2 Simulation of Non-idealities on Modulator Performance	44
6. 3 Simulation of Output Spectrum and dynamic range	45
7 Measurement Results	48
7. 1 Chip Photograph	48
7. 2 Measurement Setup	49
7. 3 Measurement Results of Sigma-Delta Modulator	51
8 Summary	54
Chapter 4 Design of Decimation Filter 55
1 Introduction	55
2 System Description and Specifications	55
2. 1 DC Offset Correction	56
2. 2 CIC Decimation Filter	57
2. 3 Halfband Filter	59
3 Implementation of Decimation Filter	62
3. 1 Truncation of Insignificant Bits	63
3. 2 Overflow Condition	64
3. 3 1-bit Full Adder	65
3. 4 D Flip-Flop Circuit	66
3. 5 1-bit Integrator and Differentiator	67
3. 6 Cascaded Integrator and Comb Filter	68
3. 7 Halfband Filter Design	69
4 Layout consideration	71
5 Simulation Results of Sigma-Delta ADC Chip	72
5. 1 Transient Simulaton	72
5. 2 Simulation of Halfband Filter and CIC Filter	72
5. 3 Simulation of Output Spectrum and Dynamic Range	73
6 Summary	79
Chapter 5 Chip Design of the CT Quadrature Bandpass Sigma-Delta Modulator with Capacitive Feedback 81
1 Introduction	81
2 Complex Bandpass Modulator	82
2. 1 Complex Filter	82
2. 2 Complex Noise Transfer Function	82
2. 3 Complex ΔΣM Architecture	83
3 Design of the Continuous Time Complex Bandpass Delta Sigma Modulator	84
3. 1 Lowpass Loop Filter with CICFF Architecture	84
3. 2 Polyphase Quadrature Bandpass Loop Filter	84
3. 3 Modulator Circuit Design	85
3. 4 Continuous-Time Quadrature Bandpass ΣΔ Modulator	86
4 Circuit Implementation	87
4. 1 Tunable Capacitor Array	87
4. 2 Op Amp	88
4. 3 Bias Circuit	88
4. 4 Quantizer, D-Latch, and DAC Circuits	89
5 Effects of Non-Idealities on Modulator Performance	90
5. 1 Effect of Non-Ideal Opamp	90
5. 2 RC Product Variation	91
5. 3 Clock Jitter	91
5. 4 Channel Mismatch	92
6 Layout	92
7 Simulation Results	93
8 Measurement Result	95
9 Summary	100
Chapter 6 Conclusions and Future Work 101
Reference 103
Appendix  108

                                

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