隨著電子產業的演進,傳統的金氧半元件將面臨微縮化後產生的一些可靠度問題,例如短通道效應、熱載子效應、閘極引起汲極漏電流。由於穿透式場效電晶體的工作原理與傳統金氧半元件有所不同,因此在高度微縮化後,較無這些通道微縮化所造成的可靠性問題。
針對穿透式場效電晶體,到目前為止仍有一些需要被解決的問題。此論文的目的就是透過元件結構改變及其相關參數模擬分析來實踐獲得高性能的穿透式場效電晶體。關於元件結構改變部份,主要有源極區增加輕摻雜的新設計與源極區內新增n型重摻雜的新設計。從模擬分析的結果來看,元件結構的新設計確實較傳統穿透式場效電晶體的元件有較佳的性能提升。例如,較高的on current與較低的off current。
由於穿透式場效電晶體較無傳統金氧半場效電晶體隨著元件微缩產生的可靠性問題,而且其結構及製程與傳統金氧半場效電晶體也有相似之處，因此穿透式場效電晶體可用來當金氧半場效電晶體在未來應用上理想的替代性元件。

In the progress of the electronics industry, the scaled down of the conventional MOSFET device will emerge some reliability problems, such as short-channel effect, hot-carrier effect, and gate-induced-drain leakage (GIDL). Tunneling field effect transistor (TFET) has the immunity from these problems in high scaling fabrication due to its operation mechanism is different from the MOSFET device.
So far, some issues of TFET are still need to be resolved. To obtain higher-performance TFET in this study, the design of new device structure and the analysis of device relative parameters are carried out via process and device simulation. In this study, there are two newly designed TFET structures. They are “TFET with LDS (lightly doped Source) structure” and “Modified TFET structure” with n+ doping in Source. From the simulation results, the newly designed TFET structures do have better performance than the conventional TFET. For example, they have higher on current or lower off current.
Since TFET has fewer reliability problems than the conventional MOSFET device in high scaling fabrication, and TFET also has the structural similarity as MOSFET. So, the TFET can be thought of as a promising alternative to the MOSFET in the future.

[1] Woo Young CHOI, Jong Duk LEE, and Byung-Gook PARK, “Novel Tunneling Devices with Multi-Functionality”, Japanese Journal of Applied Physics, Vol. 46, No. 4B, pp. 2622–2625, 2007.
[2] 胡倍慎, “穿透式場效電晶體之研究”, 碩士論文, 國立台灣科技大學, 台北, 第1-4頁, 2007。
[3] Stanley Wolf, “SILICON PROCESSING FOR THE VLSI ERA”, Vol.3, p.559.
[4] Stanley Wolf, “SILICON　PROCESSING FOR THE VLSI ERA”, Vol.3, p.198.
[5] 施敏、黃調元, “半導體元件物理與製作技術”, 交大出版社,
第304-309頁, 2007。
[6] Stanley Wolf, “SILICON　PROCESSING FOR THE VLSI ERA”, Vol.3, p.211.
[7] S.M Sze, “SEMICONDUCTOR DEVICES physics and Technology”, second Edition, p.200.
[8] Mahdi Vadizadeh, Morteza Fathipour and Arash Amid, “A Novel Nanoscale Tunnel FET Structure for Increasing for On/Off Current Ratio”, 2008 international Conference on Microelectronics, 2008.
[9] S.M Sze, “SEMICONDUCTOR DEVICES physics and Technology”, second Edition, p.202.
[10] Shockley W. and Hopper WW, “The surface controlled avalanche transistor”, IEEE Tran. Electron Device, Vol.11, No.11, p.535, 1964.
[11] Reddick W.M. and Amaratunga G.A.J, “Gate controlled surface tunneling transistor”, High Speed Semiconductor Devices and Circuits, Vol.7, No. 9, pp.490-497, 1995.
[12] Banerjee S, Richardson W, Coleman J, and Chatterejee A, “A new three-terminal tunnel device”, IEEE Electron Device Letters, Vol.8, No. 8, pp.347–349, 1987.
[13] Koga J. and Toriumi A., “Three-terminal silicon surface junction tunneling device for room temperature operation”, IEEE Electron Device Letters, Vol. 20, No.10, pp.529-531, 1999.
[14] Bhuwalka K.K., Schulze J., and Eisele I., “Scaling the vertical tunnel FET with tunnel bandgap modulation and gate work function engineering”, IEEE Tran. Electron Device, Vol.52, No.5, pp.909-917, 2005.
[15] Uemura T. and Baba T., “Direct gate-controlled NDR characteristics in surface tunnel transistor”, Device Research Conference, Vol.20, No.22, pp.65-66, 1994.
[16] Hansch W., Fink C., Schulze J., and Eisele I., “A vertical MOS-gated Esaki tunneling transistor in silicon”, Thin Solid Films, p.369 and pp.387-389, 2000.
[17] Tehrani S., Shen J., Goronkin H., Kramer G., Tsui R., and Zhu T.X., “Resonant interband tunneling FET”, IEEE Electron Device Letters, Vol.16, No.12, pp.557-559, 1995.
[18] Aydin C, Zaslavsky A, Luryi S, Cristoloveanu S, Mariolle D
and Fraboulet D, “Lateral interband tunneling transistor in silicon-insulator” Appl Phys Lett, Vol.84, No.10, pp.1780-1782, 2000.
[19] James Towfik Teherani, “Band-to-band tunneling in Silicon Diodes and Tunnel Transistors”, Master dissertation, Massachusetts Institute of Technology, Massachusetts, U.S.A., 2010.
[20] Kathy Boucart and Adrian Ionescu, “Simulation of the Silicon Tunnel FET”, Technical Report, China, 2007.
[21] Woo Young Choi, “Comparative Study of Tunneling Field-Effect Transistors and Metal-Oxide-Semiconductor Field-Effect Transistors”, Japanese Journal of Applied Physics, Volume 49, Issue 4, pp. 04DJ12-04DJ12-3, 2010.
[22] SYNOPSYS, INC, “TSUPREM-4 Two-Dimensional Process
Simulation Program”, User Manual, 2003.
[23] SYNOPSYS, INC, “Medici”, User Guide, 2006.