本論文提供以多重元件匹配之高階梯度誤差消除的能力，來建構佈局模式的方法。有了這些方法，工程師將有更大的自由度，依據其創新和電路準確度，來選擇佈局模式。Shuffled模式是被用作為同重心之多重元件的一階佈局模式。為了實現高階梯度消除，兩個實際的方法被稱為對稱鏡射和反對稱鏡射，無論是在水平或是垂直方向皆已被提出。以多重元件匹配為例子，此佈局模式可以很容易地消除四階梯度，其擁有中度的繞線複雜度。考量到繞線成本、複雜度和面積，當佈局模式擁有三階梯度消除以及沒有複雜的繞線時，雙重鏡射shuffle模式會被選用。此外，所有的佈局模式已藉由數學推導和MATLAB模擬，證實可以消除梯度誤差。本電路四電阻匹配是以台積電 0.35μm的製程實現。量測後的結果顯示出，提出的佈局模式能達到更佳的元件匹配，且驗證了提出的方法是有效的。

This thesis provides general methodologies to construct layout patterns for multiple-device matching with high-order gradient error cancellation capability. With these general methodologies, engineers will have more degrees of freedom for choosing layout pattern according to their innovations and the degree of circuit precision. Shuffled pattern is utilized as the 1st-order layout pattern that ensures common centroid for multiple devices. To achieve higher order gradient cancellation, two practical methodologies called symmetrical mirroring and anti-symmetrical mirroring either in horizontal or vertical direction are proposed. As an example for multiple-device matching, the layout pattern can be easily extended to own up to 4th-order gradient cancellation capability with medium routing complexity. Due to routing cost, complexity and area, doubly mirrored shuffle pattern is recommended since it has 3rd-order gradient cancellation capability and not so complicated routing. In addition, all layout patterns have been verified in mathematical derivations and MATLAB simulations to ensure they have the claimed order of gradient error cancellation. A test chip for 4-resistor matching is implemented in a 0.35 μm TSMC technology. The measured results show that the proposed layout pattern achieve much better matching among devices than conventional ones and the usefulness of these proposed methodologies is thus verified.

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