由於積體電路越來越複雜、製程快速的演進、晶片裡面導線之間的距離越做越近，加上晶片也漸漸的往高頻應用，使得導線間的交互干擾(crosstalk)與導線在製程中所造成的天線效應(antenna effect)越來越受到重視，而這些因素會影響到積體電路的成本、效能與可靠度。為了能夠使晶片快速的進入市場，現在積體電路的設計多數使用電子設計自動化軟體來進行合成，但在購買這些軟體時往往要花費鉅額才能買齊重要的附加功能，例如交互干擾化簡的功能就非常的貴，但並不是所有的設計都非要用到這個功能不可，在電子業一片不景氣聲中，業者開始控管節省不必要的開支。基於上述原因，本篇論文提出針對已經使用三層金屬導線完成通道繞線的實體佈局，再對其改善天線效應以及交互干擾之研究。我們針對佈局中潛在天線效應的導線，以橋接(bridging)的方式來消除，而對於佈局中最嚴重的交互干擾問題，使用隨機(random)及貪婪(greedy)兩種策略來調整導線至不同的軌道或不同層，使得導線之間的最大交互干擾能夠儘量的減少。從6個測試案例的實驗結果顯示，本論文所提出的做法確實能夠改善通道繞線佈局裡的天線效應及交互干擾問題。因此，我們既可以節省下買這些軟體附加功能的花費，又可以兼顧改善晶片佈局的品質，可以說具備了一定程度的實用性。

Dut to more complicated design in VLSI, fast progress in fab manufacture, the interconnections between wires are placed in closer and circuits operate at higher frequencies, consequently the crosstalk between interconnection wires and antenna effect of wires caused by fab manufacture become an important consideration. These factors influence the cost, performance and reliability of VLSI. As time to market, most of the VLSI designs are currently synthesized with auto placement and route tools (APR tools). It costs lots of expense to buy these tools that include both powerful and essential options. For example, the option of the crosstalk reduction in APR tool is very expensive. But it is not necessary to use the crosstalk function of the tool to design each project. Many companies began to cost down unnecessary spending, especially in these days of depression. On the basis of above reasons, our paper proposed a study to eliminate the antenna effect and reduce the crosstalk for the post-layout after 3-layer HVH channel routing. We use“bridging”to cut the antenna segment in the channel so as to avoid the antenna effect. We also rearrange the track or layer for the critical net in the channel by“random”or“greedy”strategy in order to reduce the max crosstalk as far as possible. Experiments for 6 test cases show the proposed approach can improve both antenna issues and crosstalk problems. To be provided with specified practicality in IC design house, we could also reduce the expense of the options of APR tools and improve the quality of chip routing.

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