儘管半導體的製造技術已經進入奈米層級，導通孔失效的問題仍然無法有效地被解決；可製造性設計的方法已被用來縮短積體電路設計與半導體製造的差距，
在以元件為基礎(cell-based)的超大型的積體電路設計中，傳統的解決方法是在繞線時增加冗餘導通孔(redundant via)來改善導通孔的良率及可靠性。運用冗餘導通孔的設計在良率的改善上，會是單一導通孔的十倍到百倍之間，然而在冗餘導通孔的插入上，必須去解決第一層冗餘導通孔低插入率(redundant via1 insertion rate)的問題。此外，傳統元件庫的設計方法是透過視覺逐一去檢查幾何佈局(layout)，經由人工反覆調整的方式來達成最佳化，以人工視覺檢查及最佳化的的方法，除了非常耗費時間之外，品質上也是不可靠的。

在我們的研究中，考量的不只是設計精良的冗餘導通孔感知標準元件(redundant via-aware standard cells)也包含一個標準元件最佳化及連接點資源檢查的工具。本篇論文提出了一個創新的方法，運用以規則為基礎(rule-based)考量多型態導通孔裝置包含雙導通孔(double-via)及矩型導通孔(rectangle-via)來滿足不同製程的需。我們所提出的標準元件設計及最佳化的方法，除了有效降低元件庫設計的時間及改善佈局最佳化的品質問題，而且經過最佳化的冗餘導通孔感知標準元件庫也明顯改善冗餘導通孔的插入率。為支援越來越複雜積體電路設計的應用，一個元件庫包含上千個標準元件也日益多見；因此，透過自動化的方法比起傳統視覺檢查的方式來完成標準元件庫的佈局檢查及最佳化，是一個更有效找出標準元件第一層金屬連接點(metal 1 pins)資源的工具。

我們所提出的方法不僅解決第一層冗餘導通孔低插入率的問題，整體的冗餘導通孔插入率因此更為提高，製造良率也獲得改善，而且以規則為基礎的設計方法可以大幅地減少標準元件庫設計及最佳化時間；此外,此設計方法也可以被應用在先進製程的標準元件設計流程中。經過最佳化標準元件的面積不會增加，其元件特性也維持不變，我們所提出的設計方法不但很容易實施，而且經過最佳化的標準元件庫也適用於不同的繞線工具中。實驗結果證明，我們所設計的標準元件庫大幅地提高整體冗餘導通孔插入率。

Via failure persists despite nanometer-scale advances in semiconductor manufacturing technology. The conventional cell-based design improves via yield and reliability by adding redundant vias in routing for VLSI designs. Doing so can improve the yield by 10X-100X over those of single-via designs. DFM methods have been developed to bridge the gap between design and manufacturing. However, a low redundant via1 insertion rate must be addressed in redundant via insertion. Additionally, manual- and visual-based checks are required to locate pins and tune the geometries of layouts in conventional SC library design methods. Such tasks can be extremely time consuming and unreliable. This study concerns not only well-designed redundant via-aware standard cells but also an efficient standard cell optimizer and checker for standard cell design.

A nanometer-scale redundant via-aware standard cell library design scheme is developed for improving the redundant via1 insertion rate. The area and performance advantages of rectangle-via are shown compared to the double-via. This study considered the problems of nanometer-scale SC area and low via1 insertion rate for industrial DFM requirement. The novel features of the proposed scheme are analyzed in terms of input capacitance, delay and area for each SC library. In addition, RVLC algorithm used for pin size check, analysis of performance variability of libraries, and
routing approaches for redundant via-aware SC library design. Experimental results reveal that the proposed library considerably improves total inserted redundant vias and total inserted redundant via1s. The area difference between 4 lambda squared and 6 lambda squared (rectangle-via versus double-via) represents a threshold between no impact and a measurable impact to performance.

This work also presents an efficient redundant via-aware SC optimization scheme. The proposed rule-based method is based on an efficient layout check and optimization scheme that considers various redundant via configurations including the double-via and rectangle-via to shorten the design cycles and enhance the design quality of SCs. The optimized SCs effectively increase the redundant via insertion rate, particularly the insertion rate of via1. Modern nanometer-scale SC libraries may contain thousands of cells to satisfy complex VLSI requirements. Hence, an automatic layout checker and optimizer are more efficient than conventional visual check and manual optimization in identifying expandable metal 1 pins in libraries.

In addition to solving the problem of a low via1 insertion rate in nanometer regimes, the proposed scheme provides an efficient layout optimizer for designing standard cells. Capable of significantly reducing design time and effort, the proposed rule-based method is applicable to the SC design flow. The proposed ERVLCO method is less time consuming and more reliable than the conventional vision-based check and manual optimization methods, which may take several weeks. Consequently, by improving the pin accessibility of the standard cell layout, the presented method not only significantly increases the rate of redundant via insertion but also offers great efficiency and reliability. Moreover, the optimized library incurs no performance penalty in terms of cell area and other cell characterization and thus should be compatible with commercially available routers. Experimental results indicate that the optimized SC library increases the double-via1 insertion rate by 21.9%. With the rectangle-via pattern, achieves a redundant via1 insertion rate of 100%.

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