研究生: |
卓錦昌 Chin-Chang Cho |
---|---|
論文名稱: |
新平面閘流體元件(FPoT)之設計 The design for Full planar of Triac device (FPoT) |
指導教授: |
莊敏宏
Miin-Horng Juang |
口試委員: |
張勝良
Sheng-Lyang Jang 李志堅 Chih-Chien Lee |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
論文出版年: | 2018 |
畢業學年度: | 106 |
語文別: | 英文 |
論文頁數: | 79 |
中文關鍵詞: | 閘流體功率元件 、新型全平面結構設計閘流體 、P 場環設計 、N+ 場塞設計 |
外文關鍵詞: | Power thyristor components, planar structure design of Triac device, n+ field stopper design, A field ring P- design |
相關次數: | 點閱:154 下載:0 |
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閘流體功率元件現在被廣泛地應用在家電與工業電路運用上,隨電子產業進步,傳統型的閘流體元件面臨一些可靠度與偏壓運用提高的問題,例如高溫時漏電過高,信賴性 HTRB @ 150℃ & 800V 造成元件失效 。 然而,新型全平面結構設計閘流體可以提供較高的雙向偏壓,較小的高溫漏電能力,進而解決傳統結構因現在運用而造成問題。
閘流體功率元件它們靠著元件NPNP 層結構 組成Anode and cathode 通道 與 Gate閘極通道觸發電流來導通元件。然而,在傳統的閘流體功率元件的標準製程中,是須要使用silicon etching ( Mesa )的光罩;之中包含了場氧化層、溝臺蝕刻、玻璃光罩 (glass photo ) 等的光罩。一般傳統製程都需要 mesa etch 和 玻璃光罩,然而本論文中我提出一新型全平面結構設計閘流體功率元件、不需要 mesa etch 和 玻璃光罩步驟,藉由減少元件的光罩來達成本的效益。並且大大提昇高溫特性,漏電流降低與偏壓提高33% 。
在更多的應用中強化其可靠性。從高溫和反向偏壓模擬中,這種新工藝和結構與標準產品(雙檯面結構)比較,更允許在結溫150°C時, 偏壓固定在 800 V AC 運作使用時其高溫洩漏時的器件壽命可更長, 在本論文中,是透過元件結構改變,以及相關參數模擬分析來獲得高性能的全平面結構設計閘流體功率元件,為提昇雙向崩潰電壓Forward blocking voltage (VDRM) , Reverse blocking voltage (VRRM) ,與降低高溫漏電流(High temperature leadage) 問題 。
Power thyristor components are now widely used in home appliances and industry application. In the progress of the electronics industry , the scale down of conventional Thyristor semiconductor (Triac) will emerge some reliability and high voltage application problem, such as high temperature leakage issue and a set of high temperature and reverse bias (HTRB) tests problem @ 150 ℃ and breakdown voltage 800V to cause device be failed.
However, the new planar structure design of Triac device can provide higher breakdown voltage at both Reverse blocking and forward blocking ( VRRM & VDRM) and very low leakage performance at high temperature conditions which it will to improve application issue for conventional Thyristor semiconductor (Triac).
The basic structure for an N+–P–N–P+ power thyristor to constitute Anode / Cathode and a gate channel to turn on device by a trigger current .
However, in conventional Thyristor semiconductor (Triac) of wafer process, it is must to use silicon etching (mesa etch) of mask, all of including oxide layer, mesa tech, glass photo mask etc.
In this thesis, a new full planar structure design for power Triac device which it’s not to apply both mesa etching and glass photograph layer to eliminate and reduce process cost. Also greatly improve the characteristic of high temperature performance, leakage reduction and breakdown capability will be increased 33 %.
Strengthen its reliability in more severe applications. From a set of high temperature @ forward and reverse bias simulation, this new process and structure is allows multiplying the device lifetime compared to standard products (Double mesa structure or Top glass planar structure) at high temperature leakage when junction temperature and bias are fixed to 150 °C and 800 V AC respectively.
In this thesis, a high-performance full-plane structure thyristor power device is obtained through structural changes of components and related parameter simulation analysis. In order to improve the bidirectional breakdown voltage , forward blocking voltage (VDRM), and Reverse blocking voltage (VRRM) to reduce high Temperature leakage Problem .
[1] Sébastien Jacques, Samuel Ménard, Gaël Gautier , 2014. New field stopper process to strengthen double mesa glass AC switches reliability during rugged application environments. Advances in microelectronic engineering (AIME) vol.2, issue 3 : 1-8
[2] Josef L. Heinrich, S. Uwe S, Rik D. D. 2011 “Semiconductor power devices physics, Characteristics, Reliability” .P. 257. Springer-verlag berlin heidelberg.
[3] Yong L , 2012. Fairchild Semiconductor Corporation " Power electronic packaging design, assembly process, reliability and modeling" . pp.1-7, Springer science business media, LLC .
[4] B. J. Baliga . 2008. “Fundamentals of power semiconductor devices”. P.628. Springer science + business media, LLC.
[5] B. J. Baliga. 1996. “ Power semiconductor device “ . P260 , North Caroline state university.
[6] Adolph B. 1976 “ Thyristor Physics “ .p8, Springer – verlag ,
[7] PAUL D.T. 1987 “Thyristor design and realization” .p72 , Marconi electronic devices Ltd.
[8] Josef L. Heinrich, S. Uwe S, Rik D. D. 2011 “Semiconductor power devices physics, characteristics, reliability” . P. 142. Springer-verlag berlin heidelberg.
[9] Vitezslav B, John G, Duncan A. G. 1999 “ Power semiconductor devices theory and application “ p118.
[10] Vitezslav B, John G, Duncan A. G. 1999 “ Power semiconductor devices theory and application “ p. 123.
[11] Sébastien J, Samuel M, Gaël G . 2014 “New field stopper process to strengthen double MESA-GLASS AC switches’ reliability during rugged application environments” , p.3.
[12] J E. E. 2014, A study of field-ring design using a variety of analysis method in insulated gate bipolar transistor (IGBT)” , Vol. 9 : p.1 .
[13] J E. E. 2014, A study of field-ring design using a variety of analysis method in insulated gate bipolar transistor (IGBT)” , Vol. 9 : pp.1-9 .
[14] C. Basavana Goud, Member, IEEE, and K. N. Bhat , 1991 .Two-dimensional analysis and design considerations of high-voltage planar junctions equipped with field plate and guard ring” , , vol 38 : p.11.
[15] Tomowki T., Yasuhiro M, and Masahiro O, 1980, Analysis of a junction termination structure for ideal breakdown voltage in p-n junction devices”, p. 5.
[16] Eun S. J, Sin-su K and Ey G K , 2015 , A Study of field-ring design using a variety of analysis method in insulated gate bipolar transistor (IGBT) Vol. 9, No. 742. p.2.