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| 研究生： |
徐國倫 Kuo-Lun Hsu |
|---|---|
| 論文名稱： |
設計與實現一個基於AXI3介面的DDR4-SDRAM控制器 The Design and Implementation of an AXI3-Interface-Based DDR4-SDRAM Controller |
| 指導教授： |
林銘波
Ming-Bo Lin |
| 口試委員: |
陳郁堂
Yie-Tarng Chen 林昌鴻 Chang-Hong Lin 林敬舜 Ching-Shun Lin 林銘波 Ming-Bo Lin |
| 學位類別： |
碩士 Master |
| 系所名稱： |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
| 論文出版年： | 2018 |
| 畢業學年度： | 106 |
| 語文別： | 中文 |
| 論文頁數： | 78 |
| 中文關鍵詞： | 記憶體控制器 、DDR4-SDRAM 、AMBA AXI3 |
| 外文關鍵詞： | DDR4 SDRAM, AMBA AXI3, SDRAM Controller |
| 相關次數： | 點閱：124 下載：12 |
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隨著科技進步，SoC (System on Chip) 功能日趨複雜而效能越來越高，對記憶體的的需求也越來越大，因此記憶體是現今SoC不可或缺的一環。然而，其存取速度卻遠低於處理器。因此，若要增加SoC的效能，就需改善記憶體的效能。為此，需要設計一個能有效率的協調處理器與記憶體，並大幅改善記憶體效能的記憶體控制器。
本論文設計一個符合AMBA AXI3介面的記憶體控制器。AMBA AXI系列為ARM公司提出的介面協議。它植基於爆發 (Burst) 式交易數據傳輸，並擁有讀、寫獨立通道，可以提高設計效率、更具彈性，並且易於與其它SoC整合。記憶體控制器利用DDR4 SDRAM內建的Auto precharge功能，達到節省下達指令時間，以利於將指令高效率排程，並依照DDR4 SDRAM各種不同狀況，依照規定的時間參數需求，做最低限度的延遲，以提高效能。利用DDR4 SDRAM本身架構優勢及功能做設計，在不更改過多硬體架構前提下，能優化指令排程，有效減少延遲，因而提升記憶體的存取效能。
完成的記憶體控制器符合DDR4 SDRAM和AMBA AXI3 的標準規範。它可以依照不同的情況，做最低延遲後，正確地存取資料。在Xilinx Virtex6 開發板上實現時，總共消耗1496個LUT及1358個暫存器，操作頻率最高可達225.073MHz。
With the advance of science and technology, the functionality of system-on-chip (SoC) has become more complex, and the performance is higher and higher, leading to the increasing demand of a large amount of memory. As a consequence, the large-capacity memory is indispensable to current SoCs. Unfortunately, the memory access speed is far below the processor’s speed and hence limits the performance of the system. Hence, to promote the performance of SoCs, it is necessary to design an efficient memory controller to coordinate the operations between the processor and memory modules so as to reduce the memory access time.
In this thesis, a memory controller compliant with the AMBA-AXI3 interface specifications is designed. The AMBA AXI3 based on burst transactions has independent reading and writing channels; thus, it is much more flexible and efficient, and can be easily to integrate with other SoCs. The memory controller uses the built-in auto-precharge function of DDR4 SDRAM to save the commanding time, and therefore its access operations can be highly efficient. In addition, it can follow timing parameters to do the lowest limit delay to improve performance according to the different situations of DDR4 SDRAM. By using the advantages of DDR4-SDRAM’s architecture and functions, we optimize the schedule of commands and reduce the delay to improve the memory performance.
The design of memory controller is in accordance with the DDR4-SDRAM and AMBA-AXI3 specifications. It not only can properly write/read data after the lowest limit delay according to different DDR4-SDRAM situations but also meet the timing of DDR4-SDRAM’s specifications. The DDR4-SDRAM controller implemented with Xilinx Virtex6 XC6VCX75T consumes 1496 LUTs (Look Up Table) and 1358 registers. Its maximum operating frequency is 225.073MHz.
[1] “AMBA® AXI and ACE Protocol Specification-AXI3, AXI4, AXI5, ACE and ACE5,” ARM, 2017.
[2] “DDR4 SDRAM MT40A1G4 MT40A512M8 MT40A256M16,” Micron Technology, 2014.
[3] Yu Zhang, Ming Ling, Hanlai Pu, and Fan Zhou, “Performance Exploration and Optimization of SDRAM-Controller Architecture on SDRAM Access,” IEEE International Conference on ASIC, pp.247-250, Oct. 2005.
[4] T. Y. Oh et al., “A 7 Gb/s/pin GDDR5 SDRAM with 2.5 ns bank-to bank active time and no bank-group restriction,” IEEE ISSCC Dig. Tech. Papers, pp. 434-435, 2010.
[5] “DDR4 SDRAM Specification (JESD79-4),” JEDEC solid state technology association, September 2012.
[6] “Synthesizable DDR SDRAM controller Application note,” Xilinx Inc., XAPP200, 2002.
[7] “Ultra Scale Architecture-Based FPGAs Memory IP v1.2,” Xilinx Inc., June 8, 2016.
[8] 黃文詮，AMBA 相容之動態記憶體控制器智財設計與驗證，國立台灣科技大學，電子工程系，碩士論文，西元2009年11月.
