本論文主要是設計一個切換式電流模式控制昇壓型穩壓器IC，其具有1伏啟動功能，可使用單顆鎳氫(NiMH)電池的電壓(約1.2 V)昇壓至2 ~ 6 V；15 uA低靜態電流，在無載時可以延長電池使用時間；依據負載電流大小自動切換脈衝寬度調變(Pluse Width Modulation, PWM)和脈衝頻率調變(Pluse Frequency Modulation, PFM)兩種調變技術，可以使輕載和重載時一樣有高的轉換效率，適合用於可攜帶式電子產品。
本論文中所提出的切換式昇壓型穏壓器IC，內部包含了能隙參考電壓源、史密特觸發器、過溫/過電流保護、比較器、時脈產生器、斜率補償電路、驅動電路以及數位控制邏輯電路。此晶片是以華潤上華(CSMC)公司點五微米五伏互補式金氧半製程來實現，所占用之晶片面積尺寸為0.6×0.8 mm2，而工作電壓的範圍為2 ~ 6 V，最低啟動電壓為0.95 V，負載調整率和輸入電壓調整率分別為1.3283 mV/mA和0.5 mV/V，其他的量測結果也包含在本論文內。

This thesis aims to design a switching boost regulator IC with 1-V start-up feature. It can boost the input voltage from single NiMH battery (around 1.2 V) to 2 ~ 6 V. With a 15-贡A ultra low quiescent current at no load, the battery lifetime can be extended. Depending on the load level, the pulse width modulation (PWM) and pulse frequency modulation (PFM) schemes can be automatically switched to ensure high conversion efficiencies at light and heavy loads. Thus the proposed boost regulator IC is suitable for portable electronic device applications.
The presented switching boost regulator IC contains a bandgap reference voltage source, a schmitt trigger, over temperature/over current protections, comparators, a clock generator, a slope compensation circuit, a driver circuit and digital control logic circuits. This chip is implemented by CSMC’s 0.5-贡m/5-V CMOS process. The chip area is 0.6×0.8mm2 and the operating voltage lies in the range of 2 to 6 V. The minimum start-up voltage is 0.95 V. The load regulation and line regulation are respectively 1.3283 mV/mA and 0.5 mV/V. Other measurements are also included.

[1] Chi Yat Leung, Philip K. T. Mok and Ka Nang Leung, “A 1-V Integrated Current-Mode Boost Converter in Standard 3.3/5-V CMOS Technologies” IEEE J. Solid-State Circuit, vol. 40, no 11, pp. 2265-2274, Nov. 2005.
[2] Chester Simpson, “Linear and Switching Voltage Regulator Fundamentals”, National Semiconductor Application Note. 1999.
[3] Application Report, SLVA072, “Technical Review of Low Dropout Voltage Regulator Operation and Performance”, TI, August, 1999.
[4] Robert W. Erickson and Dragan Maksimović, Fundamentals of Power Electronic, 2nd ed., Kluwer Academic Publishers, 2000.
[5] Ned Mohan, Tore M. Undeland, and William P. Robbins, Power Electronics: Converter, Applications, and Design, John Wiley & Sons, 3rd Edition, 2003.
[6] Robert W. Erickson, “DC-DC Power Converter,” article in Wiley Encyclopedia of Electrical and Electronics Engineering.
[7] Robert Mammano, “Switching Power Supply Topology: Voltage Mode vs. Current Mode,” Texas Instruments Inc., Dallas, TX Unitrode Design Note DN-62, 1994.
[8] Ray Ridley “Current mode or voltage mode?” Switching Power Magazine, pp. 4-5 Oct. 2000.
[9] Doug Mattingly, “Designing Stable Compensation Networks for Single Phase Voltage Mode Buck Regulators,” Intresil Corporation, Dec. 2003.
[10] “Modeling, analysis, and compensation of the current-mode converter,” Texas Instruments Inc., Application Note U-97, 1999.
[11] Cheung Fai Lee and Philip K.T. Mok, “A Monolithic Current-Mode CMOS DC-DC Converter With On-Chip Current-Sensing Technique,” IEEE J. Solid-State Circuit, vol 39, no. 1, pp 3-14, Jan 2004.
[12] 陳秋麟、林振宇、楊大勇，「降低切換式電源之待機功率損失」，崇貿科技術專欄，民國92年。
[13] Everett Rogers, “Understanding Boost Power Stages in Switchmode Power Supplies,” Texas Instrument, Incorporated, Dallas, TX, Application Note SLVA061, 1999.
[14] Raymond B. Ridley, “A New Small-Signal Model for Current-Mode Control”, PhD Dissertation, Virginia Polytechnic Institute and State University, November, 1990.
[15] 林瑞禮，回授補償控制理論與實作，財團法人自強工業科學基金會，96年03月30日至96年04月01日。
[16] I. M. Filanovsky and H. Bakes, “CMOS Schmitt Trigger Design” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEM-1: FUNDAMENTAL THERY AND APPLICATION, VOL. 41, NO. 1, JANUARY 1994
[17] Phillup E. Allen and Douglas R. Holberg, “CMOS Analog Circuit Design,” Oxford university press, 2002.
[18] http://www.circuitsage.com/voltage_references
[19] Ka Nang Leung and Philip K. T. Mok, “A sub-1-V 15-ppm/℃ CMOS bandgap voltage reference without requiring low threshold voltage device,” IEEE J. Solid-State Circuit, vol. 37, no. 4, pp. 526-530, Apr. 2002.
[20]Masakazu Kiryu, Yokosuka, Hiroyuki Koinuma, Kiminobu Suzuki, both of Yokohama, all of Japan, “Reference potential generating circuit”, US Patent 4,833,342, May 23, 1989.
[21] Robert A. Blauschild, Patrick A. Tucci, Richard S. Muller and Robert G. Meyer, “A new NMOS temperature stable voltage reference,” IEEE Journal of Solid State Circuits, vol. SC-13, pp. 767-774, December 1978.
[22] Ka Nang Leung and Philip K. T. Mok, “A CMOS Voltage Reference Based on Weighted ΔVGS for CMOS Low-Dropout Linear Regulators,” IEEE Journal of Solid-State Circuits, vol. 38, pp. 146-150, Jan 2003.
[23] Mamoru Ugajin and Tsuneo Tsukahara, “A 0.6V Voltage Reference Circuit Based on ΣVTH Architecture in CMOS/SIMOXZ,” IEEE Symposium on VLSI Circuit, 2001.
[24] Giuseppe De Vita and Giuseppe Iannaccone, “An Ultra-Low-Power, Temperature Compensated Voltage Reference Generator,” IEEE Custom Integrated Circuits Conference, 2005, pp. 751-754.
[25] Roubik Gregorian, Introduction to CMOS OP-AMP and Comparators, New York: Wiley, 1999.
[26] K.N. Leung, C.H. Lo, P.K.T. Mok, Y.Y. Mai, W.Y. Leung and M.J. Chan, “Temperature-compensated CMOS ring oscillator for power-management circuits,” Electronics Letters 19th July 2007 Vol.43 No.15.
[27] Per Finnstam and Mikael Soderlund, “Design of CMOS ring oscillator” Master’s Thesis 2005 Chalmers University of Technology Göteborg.
[28] R. Jacob Baker, CMOS: Circuit Design, Layout, And Simulation, 3rd Edition. A JOHN WILEY & SONS, INC., PUBLICATION, 2010, pp. 344-347.
[29] Surya Musunuri and Patrick L. Chapman, “Optimization of CMOS Transistor for Low Power DC-DC Converters,” IEEE Power Electronics Specialists Conference, 2005: 2151-2157.
[30] Philip MoK, “Design of Power Management IC - Voltage Reference, Low-Dropout Regulator and Switching Regulator,” 2005 混合訊號式積體電路設計專題研討會, June 16-17, 2005.
[31] Labros Bisdounis, Spiridon Nikolaidis and Odysseas Koufopavlou, Propagation Delay and Short-Circuit Power Dissipation Modeling of the CMOS Inverter, IEEE Transactions on Circuit and System-I: Fundamental Theory and Applications, Vol. 45 No. 3, March 1998.
[32] Atila Mertol, “Estimation of Aluminum and Gold Bond Wire Fusing Current and Fusing Time,” IEEE Transactions on Electronics Packaging Manufacturing Technology Part B, Vol. 18, No. 1, February 1995.
[33] Eugene Loh, “Physical analysis of data on fused-open bond wires,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Vol. CHMT-6, No. 2, June 1983.
[34] Aditi Mallik and Roger Stout, “Simulation Methods for Predicting Fusing Current and Time for Encapsulated Wire Bonds,” IEEE Transactions on Electronics Packaging Manufacturing, Vol. 33, No. 4, October 2010.
[35] Behzad Razavi, “Design of Analog CMOS Integrated Circuits,” Boston, MA: McGraw-Hill, 2001.
[36] Inder Bahl, “Lumped Elements for RF and Microwave Circuits,” Artech House, PP. 146-160, 2003.
[37] George Harman, “Wire Bonding in Microelectronics,” 3rd edition. New York: McGraw-Hill, 2010.
[38] H. M. Greenhouse, “Design of Planar Rectangular Microelectronic Inductor,” IEEE Transactions on Parts, Hybrids and Packaging, pp. 101-109, June 1974.
[39] Poki Chen, “Analog IC Layout”, Electronic Department, National Taiwan University of Science and Technology Summer 2007.
[40] Alan Hastings, The Art of Analog Layout, Prentice Hall International, Inc., 2001.