科技的進步帶動了製程技術的演進，使得行動裝置與高密度的記憶體得以快速發展，因此人們對於非揮發型記憶體的需求也隨之成長，而在眾多的非揮發型記憶體當中，電阻式記憶體具有較快的操作速度、較低的功耗以及更高的密度，然而，電阻式記憶體的製程技術尚未成熟，加上憶阻器本身固有的特性，使得電阻式記憶體面臨良率與可靠度方面的問題。此外，記憶體製程的微縮造成內部線路電阻的上升，使記憶體在正常操作時可能會因為線路電阻產生的壓降導致其操作失敗，此現象會隨著記憶體陣列越做越大而變得更加嚴重。為了維持記憶體的良率與可靠度，過去所提出的研究大多是利用錯誤更正碼與內建自我修復技術來進行修復，但額外增加的硬體成本卻成為了一大負擔。
有鑑於此現象，本篇論文首先針對電阻式記憶體的故障模型進行分析，利用 March W-1T1R 測試演算法與本篇論文所提出的故障字典，將故障重新分類為存 0 與存 1 安全故障，同時結合位址重映射技術來提升故障遮蔽的機率。舉例來說，一個固定於邏輯 0 的故障，在資料存取時只要寫入邏輯 0 即可避免故障被激發，因此在資料進行寫入前，利用位址重映射技術改變資料邏輯與實體位址間的對應關係，讓安全的邏輯值寫入故障之記憶體細胞中，即可有效的減少故障發生的數量。
本篇論文實現了位址重映射技術的電路，並利用 Python Tkinter 模組開發了模擬器，實現位址重映射演算法並以此評估記憶體的修復率與良率，同時推導出此技術的可靠度公式與額外增加的硬體成本。實驗結果顯示在 1 GB 電阻式記憶體中，當正交故障為 70% 時，位址重映射技術之修復率相較於 BCH3 碼提升了約 40%，而在原始良率為 0.85時，有效良率皆可維持在 99% 以上，可靠度於 70 萬小時後仍能維持在 90% 以上，額外增加的硬體成本則幾乎可以忽略。

Due to the advance of process technology, mobile devices and high density memories are being developed rapidly. Therefore, the demand on non-volatile memory (NVM) keeps increasing steadily. Among these emerging NVMs, the resistive RAM (RRAM) has the features of faster operation speed, lower power consumption and high density than other emerging NVMs. However, due to the immature fabrication technology and the intrinsic nature of memristors, it would cause yield and reliability problems. Besides, the shrinked memory feature size also induces side effects in terms of reliability and performance. Theses include an increase in the line resistances and a voltage drop along the line during memory operation. The voltage drop prevents memory cells from operating properly. These issues exacerbate at larger memory array sizes. To maintain the yield and reliability of RRAMs, error correction code (ECC) and built-in self-repair (BISR) techniques are widely used in the past. However, the incurred extra hardware overhead becomes a big burden.
To cure these drawbacks, we first analyze the fault behaviors of RRAMs and propose the fault dictionary for the March W-1T1R algorithm in this thesis. Based on the fault behaviors of RRAMs, we can reclassify the fault models into the 1-safe and the 0-safe fault types at the logic level. At the same time, we propose the address remapping techniques for enhancing the fault masking probability. By writing safe logic values into faulty cells, the fault effects can be effectively mitigated.
The corresponding hardware architecture of the proposed address remapping technique is also proposed in this paper. We use the Python Tkinter module to develop a simulator for implementing the address remapping algorithm to evaluate the repair rate and yield of the memory. We also derive models for evaluating reliability and hardware overhead. Experimental results show that for an 1-GB RRAM with 70% orthogonal faults of the injected faults, the repair rate can be raised by 40% as compared with the BCH3 code. When the original yield is 0.85, the effective yield can be raised to about 99%. Moreover, the reliability can be above 90% after 700,000 hours of operations. The hardware overhead for implementing the address remapping technique is almost negligible.

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