研究生: |
劉邦祐 Pane-you Liu |
---|---|
論文名稱: |
和差調變式D類數位功率放大器 Sigma-Delta Modulated Class-D Digital Power Amplifier |
指導教授: |
楊博清
Po-Ching Yang 謝冠群 Guan-Chyun Hsieh |
口試委員: |
陳建富
Jiann-Fuh Chen 劉志文 Chih-Wen Liu 蔡清池 Ching-Chih Tsai |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
論文出版年: | 2005 |
畢業學年度: | 93 |
語文別: | 中文 |
論文頁數: | 55 |
中文關鍵詞: | 數位功率放大器 、和差調變 |
外文關鍵詞: | Class-D, Sigma-Delta Modulated |
相關次數: | 點閱:313 下載:0 |
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本研究提出以和差調變技術(Sigma-Delta Modulation)為基礎的D類功率放大器(Class-D Power Amplifier)。和差調變控制器係由一週期性比較積分迴路所構成,主要架構包含積分器、取樣保持電路及比較器等,和差調變器可依參考信號轉換為適當的連續脈波信號,作為驅動開關用。功率放大器的功率級採用半橋架構,藉由上側和下側驅動電路驅動;再經LC濾波器輸出至負載。本研究實際設計製作一部100W功率放大器,輸出頻率範圍為20~20kHz,輸出效率平均87%以上,諧波失真度4%以下。
A Class D power amplifier by sigma-delta modulation (SDM) is proposed. Cycle-by-cycle control loop is adopted in converting the analog signal into a digital one. Except a constant pulse time to detect the sampled input signal level, a duty period is generated by a discharging/charging rate generated in SDM and its length is dependent on the detected input level and is a multiple of the constant sampling pulse time. Signal process and system model for converting the analog signal into digital one through the SDM modulator is explored. A prototype of 100W class D power amplifier is examined for assessing the theoretical investigation and practicality. The power efficiency is over 87%. The total harmonic distortion (THD) measured without EMI filter is less than 4%.
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