簡易檢索 / 詳目顯示
| 研究生： |
鍾登皓 Deng-Hao Zhong |
|---|---|
| 論文名稱： |
三種快速鎖定演算法適用寬頻操作且具有責任週期校正之全數位延遲鎖定迴路 A Wide-Range All-Digital Delay-Locked Loop Using Three kinds of Fast-Lock Binary Search Algorithms with Duty Cycle Correction |
| 指導教授： |
楊湰頡
Rong-jyi Yang |
| 口試委員: |
姚嘉瑜
Chia-Yu Yao 張湘輝 Hsiang-Hui Chang 韓松融 Sung-Rung Han 莊基男 Chi-Nan Chuang 陳超群 Chao-Chyun Chen |
| 學位類別： |
碩士 Master |
| 系所名稱： |
電資學院 - 電機工程系 Department of Electrical Engineering |
| 論文出版年： | 2010 |
| 畢業學年度： | 98 |
| 語文別： | 中文 |
| 論文頁數： | 76 |
| 中文關鍵詞： | 延遲鎖定迴路 、二元搜索法 、遞迴二元搜索法 、延遲線 、動態頻率調整 |
| 外文關鍵詞： | ADDLL, DLL, RSAR, FVSAR, DCDL, DVFS, Over clock, LDSAR |
| 相關次數： | 點閱：206 下載：13 |
| 分享至: |
| 查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
隨著CMOS製程技術的進步，記憶體的複雜度及時脈訊號頻率均迅速增加，因此，系統內部同步時脈訊號之可靠度便愈來愈重要。如何消除時脈偏移的問題，將成為重要的議題。
延遲鎖定迴路廣泛地運用在時脈同步的問題上，因為與傳統的鎖相迴路相比，它無條件穩定、且有較快的暫態反應，同時有較少的抖動累積現上。然而，它主要的缺點就是操作的頻率範圍較窄，同時沒有電源雜訊壓制的特性。因此全數位可調變長度二位元演算法的出現解決了上述的問題，但卻又使鎖定時間增加。所以本論文的主軸就是要克服上述所有問題點，打破傳統限制，並為延遲鎖定迴路提供一個具有彈性的應用層面。
本輪文提出了全數位延遲鎖定迴路，利用三種改良式二位元演算法來加速鎖定時間的。首先提出快速鎖定可調變二位元演算法，主要針對可調變演算法在搜索時發生的重複性搜索做排除，藉此來縮短鎖定時間。其次提出了遞迴式二位元演算法，期望在位元長度上的搜索中，呈現非單調遞增使高低頻搜索時間一致，但遞迴式二位元演算法卻讓二元搜索上重複性更加嚴重，因此也利用了快速鎖定機制來使鎖定時間大幅縮短，最後則提出了具有位元使用長度偵測機制的二位元演算法，它彌補了快速鎖定可調變二位元演算法和遞迴式二位元演算法的缺點，並且巧妙的運用其優點，使相位偵測器能夠運用在大範圍的頻率搜索，如此不但更近一步加速鎖定時間，且使相位偵測器克服非50%責任週期來達成鎖定。
With the progress of the CMOS technologies, the complexity and higher clock signal frequency of memory are increasing day after day. Therefore, the reliability of the clock signal in synchronous system becomes more and more important. How to reduce clock skew will be the most important topic of the clock synchronization circuit.
Delay-locked loops (DLLs) are widely used to solve the issue of clock synchronization due to its un-conditionally stable, faster transient response and less jitter accumulation than the phase-locked loops (PLLs). However, the narrow operating frequency range and no supply noise suppression become the major drawbacks for the DLLs. Therefore the variable successive approximation register-controlled (VSAR) algorithm [6] was reported to solve the problems, but the lock time is too long. Thus the subject of this dissertation is to overcome the defects, to break the limitations and to make a flexible use for the conventional DLLs circuit.
This paper presents an all-digital implemented delay-locked loop with a fast-lock characteristic using three modified binary search algorithms. First, the phenomenon of repetitive search in the VSAR algorithm is removed by the proposed fast VSAR (FVSAR) algorithm. Second, the recursive SAR (RSAR) algorithm applies the binary search algorithm to the delay length adjustment in the VASR algorithm. However, the phenomenon of repetitive search takes place in the RSAR algorithm as well. Therefore the fast recursive SAR (FRSAR) is proposed to speed up the locking process. Finally, the SAR Algorithm Delay-Lock Loop with Length Detection (LDSAR) resolve the FVSAR and the FRSAR algorithm shortcomings, LDSAR algorithm applies the Length Detection Circuit to speed up the locking time and the wide range phase detector to overcome the Non 50% duty cycle problems.
[1]A. Alvandpour, R. K. Krishnamurthy, D. Eckerbert, S. Apperson, B. Bloechel, and S. Borkar, “A 3.5 GHz 32mW 150 nm multiphase clock generator for high-performance microprocessors,” in IEEE Int. Solid-State Circ. Conf. Dig Tech. Papers, 2003, pp. 112–113, 489.
[2]K. Nose, A. Shibayama, H. Kodama, M. Mizuno, M. Edahiro, and N. Nishi, “Deterministic inter-core synchronization with periodically all-in-phase clocking for low-power multi-core SoCs,” in IEEE Int. Solid-State Circ. Conf. Dig. Tech. Papers, 2005, pp. 296–297, 599.
[3]Feng Lin, Roman A. Royer, Brian Johnson, and Brent Keeth, “A Wide-Range Mixed-mode DLL for a Combination 512Mb 2.0 Gb/s/pin GDDR3 and 2.5 Gb/s/pin GDDR4 SDRAM,” IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 631-641, Mar. 2008.
[4]D. Shin, J. Song, H. Chae, K. W. Kim, Y. J. Choi, C. Kim, “A 7ps-Jitter 0.053mm¬2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2007, pp. 184-595.
[5]A. Rossi and G. Fucilli, “Nonredundant successive approximation register for A/D converters,” Electron. Letters, vol. 32, no. 12, pp. 1055–1057, Jun. 1996.
[6]G.-K. Dehng, J.-W. Lin, and S.-I. Liu, “A fast-lock mixed-mode DLL using a 2-b SAR algorithm,” IEEE J. Solid-State Circuits, vol. 36, no. 10, pp. 1464–1471, Oct. 2001.
[7]R.-J. Yang and S.-I. Liu, “A 40-550 MHz harmonic-free all-digital delay-locked loop using a variable SAR algorithm,” IEEE J. Solid-State Circuits, vol. 42, no. 2, pp. 361–373, Feb. 2007.
[8]A. Coban, M. H. Koroglu, and K. A. Ahmed, “A 2.5--3.125 Gb/s quad transceiver with second order analog DLL-based CDRs,” IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1940–1947, Sep. 2005.
[9]B. Razavi, Design of Integrated Circuits for Optical Communications. : New York: McGraw Hill, 2002, p. 284.
[10]C. N. Chuang and S. I. Liu, “A 0.5–5 GHz wide-range multi-phase DLL with a calibrated charge pump,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 11, pp. 939–943, Nov. 2007.
[11]K. Nakamura, M. Fukaishi, Y. Hirota, Y. Nakazawa, and M. Yotsuyanagi, “A CMOS 50% duty cycle repeater using complementary phase blending,” VLSI Circuits, Dig. Tech. Papers, pp. 48–49, Jun. 2000.
[12]H. H. Chang, J. W. Lin, C. Y. Yang, and S. I. Liu, “A wide range delay-locked loop with a fixed latency of one clock cycle,” IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1021–1027, Aug. 2002.
[13]R. J. Yang and S. I. Liu, “A 2.5 GHz all-digital delay-locked loop in 0.13um CMOS technology,” IEEE J. Solid-State Circuits, vol. SC-42, pp. 2338–2347, Nov. 2007.
[14]H. H. Chang, J. W. Lin, C. Y. Yang, and S. I. Liu, “A wide range delay-locked loop with a fixed latency of one clock cycle,” IEEE J.Solid-State Circuits, vol. 37, no. 11, pp. 1021–1027, Aug. 2002.
[15]A. Alvandpour, R. K. Krishnamurthy, D. Eckerbert, S. Apperson, B. Bloechel, and S. Borkar, “A 3.5 GHz 32mW 150 nm multiphase clock generator for high-performance microprocessors,” in IEEE Int. Solid- State Circuits Conf. Dig. Tech. Papers, Feb. 2003, pp. 112–113.
[16]Y. S. Kim, S. J. Park, Y.S. Kim, D. B. Jang, S. W. Jeong, H. J. Park, J. Y. Sim, “A 40-to-800Mhz locking multiphase DLL,” in IEEE Int. Solid-State Circ. Conf. Dig. Tech. Papers, Feb. 2007, pp. 306-307.
[17]H. Chae, D. Shin, K. Kim, K. W. Kim, Y. J. Choi, C. Kim, “A Wide-Range All-Digital Multiphase DLL with Supply Noise Tolerance,” in Proc. IEEE Asian Solid-State Circ. Conf., Nov. 2008.
[18]C. H. Kuo, M.F. Lin, and C.H. Chen, “A Multi-Band Delay-Locked Loop with Fast-Locked and Jitter-Bounded Features,” in Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2008.
[19]Y. Okajima, M. Taguchi, M. Yanagawa, K.Nishimura, and O. Hamada, “Digital delay locked loop and design technique for high-speed synchronous interface,” IEICE Trans. Electron., vol.E79-C, pp. 798-807, June 1996.
[20]J.-U. Wang. “The design and realization of clock synchronizer for high speed digital systems,” MS thesis, National Taiwan University, Department of Electrical engineering, June 1998.
[21]A. Chandrakason, W. J. Bowhill, and F. Fox, Design of High-Performance Microprocessor Circuit, pp.240, IEEE Press, 2001.
[22]H.-H. Chang and S.-I. Liu, “A wide-range and fast-locking all-digital cycle-controlled delay-locked loop,” IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 661–670, Mar. 2005.
[23]B. G. Kim and L. S. Kim, “A 250 MHz-2-GHz wide-range delay-locked loop,” IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1310–1321, Jun. 2005
[24]Q. Du, J. Zhuang, and T. Kwasniewski, “A low-phase noise, antiharmonic programmable DLL frequency multiplier with period error compensation for spur reduction,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 11, pp. 1205–1209, Nov. 2006.
