物聯網的快速發展使得資料交換和通訊需求大量提升，同時資料安全和隱私保護的需求也提升。具有高效和安全特性的AES-GCM被廣泛應用於資料加密和認證中，然而在物聯網中的邊緣計算或是嵌入式系統裝置之硬體資源是有限的。因此，在本論文中，我們設計與實現一個符合資源有限的物聯網環境的AES-GCM加密認證演算法之低面積的硬體架構。
為了達到低面積的需求，在AES演算法中的位元組替代轉換模組，根據硬體的資源特性，提供各自最佳化的設計方法。在FPGA中，使用直接邏輯映射的方法實現，可以節省約32.9% 的LUTs數量。而在ASIC中，使用複合場運算的方法實現，可以節省約55.6% 的等效邏輯閘數量。在GHASH模組中，為了降低硬體資源，使用Karatsuba乘法演算法實現的有限場乘法器，可以節省約50.7% 的硬體資源。
完成的AES-GCM加解密設計分別使用FPGA與ASIC實現與驗證。在FPGA實現上，使用Xilinx公司的Virtex 7系列的XC7VX330T，其合成結果之工作頻率為181.917 MHz，最高吞吐量為1293.632 Mpbs，使用2767個Registers、8801個LUTs及2815個slices。在ASIC實作上，使用tsmc 0.18 μm 製程元件庫，其合成結果之工作頻率為83.682 MHz，最高吞吐量為595.072 Mpbs，晶片核心面積為1047.345 μm× 1051.26 μm，等效邏輯閘數量約為71677個，核心功率消耗為19.1656 mW，I/O Pad功率消耗為1.4866 mW。

The rapid development of the Internet of Things (IoT) has led to a significant increase in data exchange and communication demands, along with the need for data security and privacy protection. The AES-GCM algorithm, known for its efficiency and security features, is widely used for such requirements of data encryption and authentication. Nevertheless, the hardware resources are limited in the edge-computing devices or embedded systems used in IoT. As a consequence, in this thesis we design and implement a low-area hardware architecture based on the AES-GCM algorithm in compliance with the resource-limited IoT environment.
In order to achieve the low area requirement, an optimized design method is applied for the byte substitution module in the AES algorithm, in accordance with the hardware resource characteristics. In FPGA implementation, the method of direct logic mapping reduces about 32.9% of the number of LUTs. In ASIC implementation, the method of composite field decreases about 55.6% of the equivalent gate count. In the GHASH module, a finite field multiplier implemented using the Karatsuba multiplication algorithm saves about 50.7% of the hardware resources.
The resulting architecture of the AES-GCM encryption and decryption algorithm is implemented and verified by both FPGA and ASIC technologies. In FPGA implementation, a device (XC7VX330T) of Xilinx's Virtex 7 series is used and can operate at a frequency of 181.917 MHz, achieving a maximum throughput of 1293.632 Mbps, with 2767 registers, 8801 LUTs, and 2815 slices. In ASIC implementation, the cell library of the tsmc 0.18 μm process is employed and the resulting chip can operate at a frequency of 83.682 MHz in simulation, achieving a maximum throughput of 595.072 Mbps, with a core area of 1047.345 μm × 1051.26 μm, equivalent to 71677 gates. The core power consumption is 19.1656 mW while the I/O pad power consumption is 1.4866 mW.

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