在現代化的微處理器中，皆具備嵌入式硬體模擬器的功能，因此在本論文中，我們設計與實現了一個適宜先前設計的ARM v4指令集相容的微處理器智財(Intellectual Property, IP)的嵌入式硬體模擬器巨集單元(embedded In-Circuit-Emulator Macrocell)─Proto-ARM9DMI，並且自行開發整合發展環境(Proto-ARM9DMI Integrated Developed Environment)以提供使用者除錯的介面。
在目前具備嵌入式硬體模擬器功能的微處理器，大多使用IEEE 1149.1邊緣掃描架構為嵌入式硬體模擬器的輸入輸出埠介面，Proto-ARM9DMI亦使用IEEE 1149.1標準來設計此嵌入式硬體模擬器巨集單元。基本上架構分成Proto-ARM9M、嵌入式硬體模擬器巨集單元、三條邊緣掃描暫存器串鏈(boundary- scan-chains registers)與一個測試存取埠控制器(TAP controller)。三條邊緣掃描暫存器串鏈圍繞著Proto-ARM9M與嵌入式硬體模擬器巨集單元，其中的二條邊緣掃描暫存器串鏈用來存取兩者之內部暫存器，再藉由測試存取埠控制器與JTAG介面與外部除錯器(Debugger)相互傳遞資料進而實現晶片除錯的功能。另一條邊緣掃描暫存器串鏈的功用則是測試晶片內部元件(EXTEST)或是內部核心測試(INTEST)。
Proto-ARM9DMI微處理器已分別在Xilinx的Spartan-3 XC3S1500-4FG676 FPGA以及TSMC 0.35 μm元件庫上實現。在FPGA設計部分，消耗了11346個LUT，最高操作頻率為18 MHz，並在實驗板上撘配自行開發的整合發展環境成功的驗證所有的測試程式與除錯方式。在元件庫方面，核心面積為3837.5 μm × 3844.8 μm，等效閘數(gate count)為68513閘，整體晶片面積則為5266 μm × 5266 μm，在SS（Slow NMOS Slow PMOS model）模式下操作頻率為33.33 MHz，平均消耗功率為136.6 mW~216.1 mW。

In the modern MPUs, the embeddedICE (In-circuit-Emulator) is prevalent. Therefore, in this thesis we propose an embedded-ICE macrocell to facilitate the ARM v4 ISA compatible microprocessor IP (Intellectual Property), Proto-ARM9DMI, designed previously. Moreover, we also develop an IDE (Integrated Developed Environment), the Proto-ARM9DMI IDE, to provide the user’s interface for debugging the system.
The present MPUs having embedded-ICE function usually use IEEE 1149.1 boundry scan architecture for the input/output interface of embeddedICE. Similarly, the embedded-ICE macrocell in the Proto-ARM9DMI is designed on the basis of IEEE 1149.1 standard. Basically, the Proto-ARM9DMI consists of the Proto-ARM9M, embedded-ICE macrocell, three boundry-scan-chain registers, and a TAP controller. Three boundry-scan-chain registers surround the Proto-ARM9M and the embedded-ICE macrocell. Two of which are used for accessing the registers in the Proto-ARM9M and the embedded-ICE macrocell. Through them the Proto-ARM9DMI can communicate with external debugger controlled by the TAP controller via JTAG interface. Hence, the debug function can be accomplished. The other boundary-scan-chain registers allows inter-device testing (EXTEST) or serial teseting of the core (INTEST).
Proto-ARM9DMI has been implemented and verified with Xilinx Spartan-3 XC3S1500-4FG676 FPGA and TSMC 0.35 μm cell library, respectively. In the FPGA part, it takes 11346 LUTs and operates at the maximum working frequency of 18 MHz. Furthermore, all of the testing programs and debug functions are run successfully in FPGA development board and Proto-ARM9DMI IDE. In the cell-based part, the core occupies 3837.5 μm × 3844.8 μm, which is approximately equivalent to 68513 gates, and the whole chip occupies 5266 μm × 5266 μm. Proto-ARM9DMI consumes about 136.6 mW~216.1 mW in the SS（Slow NMOS Slow PMOS model）simulation condition at the maximum working frequency of 33 MHz.

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