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研究生: 曾士瑋
SHIH-WEI TSENG
論文名稱: 數位控制應用於低輸入漣波之 無直流偏磁非對稱全橋轉換器
Input Current Ripple Reduction Asymmetrical Full-Bridge Converter without DC Bias with Digital Control
指導教授: 呂錦山
Ching-Shan Leu
口試委員: 林景源
Jing-Yuan Lin
謝耀慶
Yao-Ching Hsieh
學位類別: 碩士
Master
系所名稱: 電資學院 - 電機工程系
Department of Electrical Engineering
論文出版年: 2016
畢業學年度: 104
語文別: 英文
論文頁數: 66
中文關鍵詞: 全橋轉換器非對稱控制降低輸入電流漣波零電壓切換
外文關鍵詞: full-bridge converter, asymmetrical control scheme, current ripple reduction, zero voltage switching
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常規的全橋(FB)轉換器已被廣泛地用於高輸入電壓與高功率應用。數個控制方案被應用於全橋轉換器,如對稱的控制,相移控制,和非對稱控制。
採用對稱控制,全橋已經使用了很長時間。患有大的開關損耗,由於其硬開關操作。它會影響轉化效率並限制功率密度。
為了提高效率,不對稱的全橋(AFB)轉換成功提出代替在過去的幾十年。因為它可以實現ZVS操作,開關導通損耗顯著降低。然而,發生直流偏置導致加在變壓器的氣隙。
然而,不對稱控制全橋轉換器具有導致高頻的di/dt雜訊,即電磁干擾(EMI)問題的源之一為產生高脈動輸入電流。因此,需要大濾波器元件以衰減閾值內的雜訊。為了減少脈動輸入電流紋波,低輸入電流紋波降低(RR-AFB)轉換器沒有直流偏置在第二章還提出。
為了演示的操作原理,電路分析的可行性,並與300〜400伏的輸入電壓範圍,24V / 15A /輸出,100k Hz開關頻率所呈現的轉換器的實驗中,驗證理論分析。
為了實現ZVS的改變死區時間用不同的負載所需RR-AFB的所有負載範圍內。並利用數位控制實現死區時間隨著不同的負載變化。


A conventional full-bridge (FB) converter has been widely used for high input-voltage high-power applications. Several control schemes have been applied to full bridge converter, such as symmetrical control, phase shift control, and asymmetrical control.
Employing symmetrical control, full-bridge has been used for a long time. It suffers from large switching losses due to its hard-switching operation. It will impact the conversion efficiency and limit power density.
To improve the efficiency, asymmetrical full-bridge (AFB) converter was successfully proposed instead in the last decades. Because it can achieve ZVS operation, the switching turn-on losses are significantly reduced. However, a DC bias occurs resulting in adding a gap on the transformer.
However, the AFB converter has high pulsating input currents resulting in the generation of high di/dt noise, which is one of the noise sources of the electromagnetic interference (EMI) problem. Consequently, large filter components are required to attenuate the noise level within the threshold value. To reduce the pulsating input-current ripple, a low-input current-ripple reduction (RR-AFB) converter without DC bias is also proposed in Chapter 2.
To demonstrate the feasibility of the operational principle, circuit analysis and the experiments of the presented converters with 300~400 V input voltage range, 24V/ 15A/ output, 100 kHz switching frequency, are built to verify theoretical analysis.
To achieve ZVS for all load range of RR-AFB needed to vary dead time with different load. The operating through analog controller cannot vary the dead time with different load, while the digital controller could. The design and implementations of the digital control for the DC-DC converters have been achieved by using the digital signal processors (DSP).

Abstract Acknowledgement Table of Content List of Figures List of Table Chapter 1.Introduction 1.1 Background and Motivation 1.2 Objectives of the Thesis 1.3 Organization of the Thesis Chapter 2. Low Input Current Ripple Reduction Asymmetrical Full-Bridge Converter without DC Bias 2.1 Introduction 2.2 Operating Principle 2.3 Circuit Analysis 2.3.1 Voltage Gain 2.3.2 Semiconductors Voltage Stress 2.3.3 Input Current Ripple Reduction 2.3.4 Zero Voltage Switching Condition 2.3.5 Duty Cycle Loss 2.3.6 Circulation Loss 2.4 Circuit Design 2.4.1 Transformer 2.4.2 Clamping Capacitor 2.5 Experimental Results 2.6 Summary Chapter 3. Design and Implementation of Digital Control 3.1 Introduction 3.2 Design of Digital 3.2.1 TMS320F28035 3.2.2 Analog-to-Digital Conversion (ADC) 3.2.3 Enhanced Pulse-Width-Modulator Module (EPWM) 3.2.4 Digital Control Flowchart 3.3 Digital Compensator 3.5 Experimental Results 3.6 Summary Chapter 4. Conclusions and Future Works 4.1 Conclusions 4.2 Future Researches Reference Vita

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