高解析度的數位類比轉換器中大多會使用校正電路改善由製程變異或佈局繞線寄生效應造成的非線性誤差，然而大多數的校正方法需要精確的量測輸出電壓的誤差值。本論文提出一種全新的校正方法來對DAC進行校正，能夠改善需要精確量測出輸出電壓的問題。在本論文中，將二十位元數位類比轉換器拆分成MSB-DAC、ISB-DAC以及LSB-DAC三個部分。MSB-DAC由溫度計編碼控制，能夠確保其單調性並且具有較低的DNL；ISB-DAC以及LSB-DAC皆由二進制控制，能夠大幅降低數位控制線的面積。LSB-DAC的解析度較低，可以不透過校正電路實現高精準度。因此將LSB-DAC用於估測MSB-DAC以及ISB-DAC每個位元的權重誤差，接著透過一個電阻式的校正數位類比轉換器對主電路進行電阻權重誤差補償以實現二十位元的準確度。
本論文利用TSMC 0.18um 1P6M CMOS製程來實現此DAC。供應電壓為3.3-V，輸出電壓範圍為0. 3 V到3 V。由後模擬結果顯示，受佈局影響，其SFDR為92 dBc。量測結果顯示，在取樣頻率為10 kS/s以及輸入碼為1 kHz的峰對峰弦波時，校正後的SFDR可改善至89 dBc。

In order to improve the nonlinear effect from PVT variation and routing, many designs have been adopted calibration schemes in high-resolution digital to analog converters (DACs). However, most of the calibration methods require precise output error voltage measurement. A novel calibration scheme is proposed in this thesis to calibrate the errors without precise voltage measurements. The proposed 20-bit DAC is divided into three parts: MSB-DAC, ISB-DAC and LSB-DAC. MSB-DAC is controlled by thermometer-code, which can guarantee monotonicity and low DNL. ISB-DAC and LSB-DAC are controlled by binary code to save layout area. The resolution of LSB-DAC is low, which means that it can achieve high accuracy without calibration. Therefore, the LSB-DAC is used to estimate the bit-weight error in MSB-DAC and ISB-DAC. A resistive calibration DAC is then used to compensate the bit-weight error in the main DAC to achieve 20-bit accuracy.
The proposed DAC is implemented in TSMC 0.18 um 3.3 V CMOS process, and the output voltage range is from 0.3 V to 3 V. The post-layout simulation results show that the SFDR is 92 dBc, worsen by layout errors. With 1 kHz sinewave input at 10 kS/s, the measurement results show that its SFDR can achieve 89 dBc after calibration.

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