本論文係有關兩階段區塊式圓形霍夫轉換演算處理系統之軟/硬體整合設計與實現，相關研究工作包含四大部分:
第一部分係兩階段區塊式圓形霍夫轉換演算法之軟體設計，在分析演算法特性並考量嵌入式系統記憶體資源的限制後，發展出兩階段區塊式圓形霍夫轉換演算法，並以C語言撰寫程式來驗證其功能之正確性。
第二部分為設計與實現兩階段區塊式圓形霍夫轉換演算處理器，其包含控制單元、來源資料暫存模組、第二階段區塊座標產生模組、投票產生模組、投票模組以及尋找區域最大值模組，並將以上硬體設計整合於可程式化單晶片系統(System on a programmable chip, SOPC)中，以Altera FPGA(Field programmable gate array)開發板實現。
第三部分為演算處理系統軟/硬體整合設計之實現與驗證，係使用NIOS II IDE(Integrated development environment)撰寫相關軟韌體程式，進行其功能之驗證與分析。
第四部分則是進行演算處理器之效能評估。
整體而言，本論文係以研究兩階段區塊式圓形霍夫轉換演算法並設計與實現其演算處理系統為目標，同時將其實現於Altera FPGA開發板上，以比較並證實本論文所發展之演算法與硬體處理器有極佳的效能。

This thesis is related to the hardware/software codesign and implementation of a two-stage block-based algorithmic processing system for the circular Hough transform. The related research work includes four parts:
The first part is about the software design of a two-stage block-based circular Hough transform algorithm. After analyzing the property of the circular Hough transform algorithm and considering about the limited memory resources in the embedded systems, a two-stage block-based circular Hough transform algorithm has been developed. In this part, C language is used to write the program for verifying this proposed algorithm.
The second part is to design and implement an algorithmic processor for the two-stage block-based circular Hough transform. The processor consists of a control unit, a source-data-buffer module, a coordinate-generator module, a votes-generator module, a voting module, and a local-max module. The custom hardware is integrated into a system on a programmable chip and implemented on the Altera FPGA development board.
The third part is related to the implementation and verification of the hardware/software codesign for an algorithmic processing system. Here, with NIOS II IDE, driver and firmware programs are written to verify and analyze the functionality of the system.
The fourth part is to evaluate the performance of the algorithmic processor.
On the whole, the goal of this thesis is to do research on a two-stage block-based algorithm for the circular Hough transform and to design and implement an algorithmic processing system for it. Meanwhile, this algorithmic processing system has been implemented on an FPGA development board to compare and prove that the algorithm and hardware processor developed in this thesis have nice performance.

[1] 陳鶴仁, SOPC-Based 演算處理器驗證系統之硬體設計, 國立台灣科技大學碩士學位論文, 民國95年。
[2] 黃健軒, HT-based直線偵測兩階段演算處理器之軟/硬體整合設計與實現, 國立台灣科技大學碩士學位論文, 民國100年。
[3] 龔柏元, 基於FPGA之單次跌待平行細線化演算法處理系統之設計與實現, 國立台灣科技大學碩士學位論文, 民國104年。
[4] 胡閎閔, 時序中值濾波背景相減演算處理系統之軟/硬體整合設計與實現, 國立台灣科技大學碩士學位論文, 民國104年。
[5] 郭立宇, CAM-based SRAM內建自我修復電路之設計與驗證, 國立台灣科技大學碩士學位論文, 民國105年。
[6] 洪維恩, C語言教學手冊, 2015。
[7] P.V.C Hough, Machine Analysis of Bubble Chamber Pictures, Proc. Int. Conf. High Energy Accelerators and Instrumentation, 1959.
[8] Duda, R. O. and P. E. Hart, “Use of the Hough Transform to Detect Lines and Curves in Pictures,” Comm. ACM, Vol. 15, pp. 11-15(January, 1972).

[9] L. G. Shapiro and G. C. Stockman, Computer Vision, Prentice Hall, 2001.
[10] Altera Corporation, NIOS Development Board Stratix II Edition Reference Manual, 2007
[11] Altera Corporation, Quartus II Handbook, 2010.
[12] Altera Corporation, Avalon Bus Specification Reference Manual, 2010.
[13] F.Ferhat-taleb Alim, K.Messaoudi, S.Seddiki and O.Kerdjidj, “Modified Circular Hough Transform using FPGA,”International Conference on Microelectronics, 2012.
[14] Xin Zhou, Yasuaki Ito, and Koji Nakano, “An Efficient Implementation of the One-Dimensional Hough Transform Algorithm for Circle Detection on the FPGA,” Second International Symposium on Computing and Networking, 2014
[15] Arif Irwansyah, Omar W. Ibraheem, Jens Hagemeyer, Mario Porrmann, and Ulrich Rueckert, “FPGA-based Circular Hough Transform with Graph Clustering for Vision-based Multi-Robot Tracking,” International Conference on ReConFigurable Computing and FPGAs(ReConFig), 2015.