隨著製程單位的下降，漏電功耗(Leakage power)已經在設計中成為一項重要的目標值，運用多個閥值電壓(Threshold Voltage)在以單位元件為基礎的設計中已經是一種流行的技術，這可以同時的優化電路時序和最小化洩電功耗。然而，在一個使用多個閥值電壓的任意佈局結果中，可能會面臨許多最小佈值區域(MIA)規則下的錯誤，因此最小佈值區域的規則是必須在詳細佈局的階段中被考慮的。目前已經存在一些研究是關於最小佈值區域規則下的詳細佈局，然而這些研究大多面臨著巨大的漏電功耗和單位元件的總位移量。我們在這篇研究中，我們會提出一重新分配閥值電壓和詳細佈局的架構，在時序限制下考慮漏電功耗和最小佈值區域規則。我們首先應用以動態規畫為基礎的演算法來重新分配閥值電壓，同時最小化漏電功耗，最小佈值區域規則下所需要預留的空間以及時序錯誤。接著在合法化(Legalization)的階段會透過單位元件的位移以及填入填充物來解決所有的最小佈值區域錯誤。實驗結果是建立於ASAP7為單位元件庫和Opencores。根據和目前研究相比的實驗結果，本篇提出的架構可以有效且有效率的降低漏電功耗和單位元件的總位移量

As the feature size decreases, leakage power consumption becomes an important target in the design, using multiple threshold voltages (VTs) in cell-based designs is a popular technique to simultaneously optimize circuit timing and minimize leakage power. However, an arbitrary cell placement result of a multi-VT design may suffer from many design rule violations induced by the Minimum-Implant-Area (MIA) rule, and thus it is necessary to take the MIA rules into consideration during the detailed placement stage. There have been some existing studies on MIA-aware detailed placement, while these works may either suffer from great leakage power overhead or large cell displacement. In this thesis, we propose a VT reassignment and detailed placement framework to consider MIA rules and leakage power minimization under timing constraints. We first apply a dynamic programming-based algorithm for VT reassignment to simultaneously minimize leakage power, the required spacings for MIA rules, and timing violations. Then, we resolve the intra- and inter-row MIA violations by cell shifting and filler insertion in the legalization stage. Experiments are conducted based on the ASAP7 cell library and Opencores. According to the experimental results compared with existing works, the proposed framework can effectively and efficiently minimize leakage power and cell displacement.

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