本論文為針對極化碼(Polar Code)之連續消除(Successive Cancellation)解碼器，在設計上以減少硬體使用率為目標，所提出的解碼器採用半平行化(Semi-Parallel)的硬體架構，藉由重複利用計算單元以降低硬體使用率，且透過分析比較半平行化的數目與解碼周期的分析，選擇出較符合效益的方式。另外在解碼後透過循環冗餘校驗(Cyclic Redundancy Check)與排序電路(Sorting)，將較容易發生錯誤的位置進行位元翻轉(Bit-Flip)，再重新進行解碼以降低解碼的錯誤率。本論文使用 MATLAB 進行演算法的開發與驗證模擬，硬體部分則使用Verilog 進行 RTL code 的撰寫，將其透過型號 Virtex7 VC707 的 FPGA 開發板進行驗證，最後將此電路透過 TSMC 40nm CMOS 製程進行硬體實現。

This dissertation proposes the design and implementation of Successive Cancellation Polar Code decoder to reduce hardware resource, which adopts a SemiParallel hardware architecture. By reusing compute units to reduce hardware resource, while analyzing the number of Semi-Parallel versus decode cycle, choose the most efficient way to design Semi-Parallel hardware architecture. In addition, after decoding, through Cyclic Redundancy Check and Sorting circuit, flip the highest error probability location and re-decode (Bit-Flip) to reduce decoding error rate.
The software simulation environment in this dissertation is MATLAB, the RTL code uses Verilog hardware description language while the FPGA verification environment is Virtex-7 VC707. Finally, this circuit is implemented in TSMC 40nm CMOS process technology.

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