隨著新一代高解析度（4K、8K）影像的普及，無線傳輸的數據量急遽增加，舊有的H.264標準在壓縮效率上已不敷使用。鑒於此趨勢，JVT組織訂定新的影像壓縮標準HEVC，以符合更高的數據壓縮率的需求。為了達到此目的，HEVC使用高計算複雜度的演算法來進行影像序列的編碼和解碼。
新的影像壓縮標準HEVC改進了舊有的編解碼工具，並設計了一些新的工具。與H.264 / AVC標準相比，HEVC的編解碼計算複雜度顯著的提升。因此，在本篇論文中，我們探索HEVC中某些工具的高度計算重複性與需要處理的大量數據之特性，設計了符合需求的去區塊濾波器硬體架構，以縮短其運算時間。此外，亦扼要地討論了濾波條件和濾波操作，以及該架構資料路徑和控制單元的實現。
本篇論文提出的去區塊濾波器硬體架構已在Xilinx Virtex 6系列的FPGA （xv6vcx130t）開發板上實現，使用的硬體資源包含2806個LUTs和579個暫存器，並且工作頻率達到100 MHz。

With the popularization of the new generation of high-resolution images (4K, 8K), the amount of data transmitted wirelessly has greatly increased. The past H.264 standard has no longer been efficient to meet the needs of data compression. In view of this trend, the Joint Video Team (JVT) organization has developed a new video compression standard HEVC to produces a higher data compression rate. In order to achieve this goal, the HEVC standard uses high-complexity algorithms to encode and decode video sequences.
Compared to the H.264/AVC standard, the new video compression standard not only improves old codec tools but also includes some new codec tools. Due to the increasing complexity of the HEVC's codec, in this thesis we design a hardware architecture of the deblocking filter, which focuses on the highly computational repeatability of certain HEVC tools and a large amount of data needed to be processed additionally for speeding up tools’ calculation. In addition, we describe the detailed filtering conditions and the filtering operations as well as the implementation of the data path and control unit of the architecture.
The hardware architecture of deblocking filter proposed in this thesis has been implemented and verified with an FPGA device (xv6vcx130t) of the Xilinx Virtex 6 family. The hardware resources used are 2806 LUTs and 579 registers, and the operating frequency reaches up to 100 MHz.

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