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研究生： 洪誌廷
Chih-Ting Hung
論文名稱： 多頻帶注入鎖定除三除頻器與電容耦合除五/六注入鎖定除頻器之設計
Muti-Band of Wide Locking Range Divide-By-3 and Capacitive Cross-Coupled Divide-By-5/6 Injection-Locked Frequency Divider
指導教授： 張勝良
Sheng–Lyang Jang
徐敬文
Ching-Wen Hsue
莊敏宏
Miin-Horng Juang
口試委員: 徐世祥
Shih-Hsiang Hsu
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2017
畢業學年度： 105
語文別： 英文
論文頁數： 131
中文關鍵詞： 注入鎖定除三除頻器 、電容耦合除五注入鎖定除頻器 、電容耦合除六注入鎖定除頻器
外文關鍵詞： Divide-By-3, Capacitive Cross-Coupled Divide-By-5 Injection-Locked Frequency Divider, Capacitive Cross-Coupled Divide-By-6 Injection-Locked Frequency Divider
相關次數： 點閱：305  下載：3 
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    • 本篇論文提出了四顆不同結構的注入鎖定除頻器，分別為三共振除三注入鎖定除頻器、電容耦合之除三注入鎖定除頻器、三注入除五鎖定除頻器以及寬除頻範圍除六注入鎖定除頻器。
    首先，我們探討一個使用台積電0.18微米製程，來呈現高注入射頻三共振除三注入鎖定除頻器。由量測得知，此除三電路有三個非重疊的頻帶，隨著注入功率的增加，高頻帶的除頻範圍也隨著變寬。當工作電壓操作在0.8伏特，注入訊號強度為 0 dBm時，可得注入鎖定頻帶為6.8 ~ 11.1 GHz，除頻比例為48.0446%。此晶片的核心功率消耗為7.064 mW，晶片面積為0.938 × 0.884 mm2。
    其次，本篇探討一個使用台積電0.18微米製程之電容交叉耦合除三注入鎖定除頻器，藉由調整MOSFET之閘極開關來取得最佳的除頻範圍與功耗達到電容交叉耦合特性。當工作電壓操作在1.05伏特，注入訊號強度為0 dBm時，可得注入鎖定頻帶為7.1 ~ 10.6 GHz，除頻比例為39.548%。此晶片的核心功率消耗為6.447 mW，晶片面積為0.985 × 0.749 mm2。
    第三，本篇探討一個使用台積電0.18微米製程，來呈現新型電容交叉耦合除五注入鎖定除頻器，它是利用三注入線性混波器架構之除頻器，輸入五倍頻的差動訊號會在輸出端產生一個四倍頻及二倍頻的訊號，已達到混波效果，當工作電壓操作在1伏特，注入訊號強度為 0 dBm時，可得注入鎖定頻帶為10.5 ~ 12.5 GHz，除頻比例為17.39%。此晶片的核心功率消耗為19.56 mW，晶片面積為1.139 × 1.0 mm2。
    最後，本篇探討一個使用台積電矽鍺0.18微米製程之寬除頻範圍之除六注入鎖定除頻器的頻率變化。此除頻器使用p-core除二注入鎖定除頻器疊接n-core除三電容交叉耦合式注入鎖定除頻器所構成，除二與除三除頻器皆被用做線性混波器。當工作電壓操作在1.6/1.2伏特，注入訊號強度為 0 dBm時，可得注入鎖定頻帶為11.2 ~ 14.2 GHz / 11.6 ~ 13.6 GHz，除頻比例為23.62% / 15.87%。此晶片的核心功率消耗為17.47 mW / 6.312 mW，晶片面積為0.988 × 1.0185 mm2。

    In this thesis, we propose four different kinds of injection-locked frequency dividers (ILFD): Divide-by-3 Injection-Locked Frequency Divider at High Injection Power, Capacitive Cross-Coupled Divide-by-3 Injection-Locked Frequency Divider, Divide-by-5 Injection-Locked Frequency Divider Using Triple-Injection Techniques, Wide-Locking Range LC Divide-by-6 Injection-Locked Frequency Divider, respectively.
    First, this thesis studies the high-injection RF property of divide-by-3 injection-locked frequency divider (ILFD) in the TSMC 0.18 μm 1P6M CMOS process. Measured data shows that the varactor-less divide-by-3 ILFD has three non-overlapped locking ranges, which is caused by the intrinsic triple-resonance resonator composed inductors and transformers and parasitic MOSFET capacitors. The high-band locking range drops as the injection power increases. At the supply voltage of 0.8 V, the divider’s free-running frequency is 3.52 GHz, and at the incident power of 0 dBm the locking range is about 4.3 GHz (48.0446%) from 6.8 to 11.1 GHz. The core power consumption is 7.064 mW. The die area is 0.938 × 0.884 mm2.
    Secondly, this thesis studies the device and circuit physics of a divide-by-3 injection-locked frequency divider (ILFD) based on capacitive cross-coupled resonator to explain the advantage of this circuit. This divide-by-3 ILFD was fabricated in the TSMC 0.18 μm CMOS process and all the active and passive circuit components were supplied by the foundry. The performance of capacitive cross-coupled ILFD is enhanced by optimally biasing the gate of switching transistor to trade the locking range and power consumption. The power consumption of the ILFD core is 6.447 mW and the locking range is from 7.1 to 10.6 GHz (39.548%) at injection power Pinj = 0 dBm. The die area is 0.985 × 0.749 mm2.
    Thirdly, a novel capacitive cross-coupled divide-by-5 injection-locked frequency divider (ILFD) is proposed and was implemented in the TSMC 0.18 μm 1P6M CMOS process. It uses triple-injection linear mixer approach. This ILFD combines one divide-by-5 ILFD with one divide-by-4 and one divide-by-2 ILFD, the divide-by-5 ILFD generate a 4th harmonic used as the input of divide-by-4 ILFD and a 2nd harmonic used as the input of divide-by-2 ILFD. At the drain-source bias VDD of 1V and at the incident power of 0dBm, the locking range of the divide-by-5 ILFD is 2 GHz, from the incident frequency 10.5 to 12.5 GHz, the percentage is 17.39%. The core power consumption is 19.56 mW. The die area is 1.139 × 1.0 mm2.
    Finally, this thesis proposes a wide locking range ÷6 ILFD designed in the TSMC 0.18 μm BiCMOS process. The proposed current-reused ILFD is based on a ÷2 p-core LC ILFD stacking on a ÷3 n-core capacitive cross-coupled LC ILFD. Injection MOSFETS in ÷2 and ÷3 ILFDs are used as linear mixers. At the drain-source bias VDD of 1.6/1.2V and at the incident power of 0 dBm, the locking range is 3/2 GHz (23.62/15.87%), from the incident frequency 11.2/11.6 GHz to 14.2/13.6 GHz. The core power consumption is 17.47/6.312 mW and the die area is 0.988 × 1.0185 mm2.

    中文摘要 Abstract 誌謝 Table of Contents List of Figures List of Tables Chapter 1 Introduction 1.1 Background 1.2 Thesis Organization Chapter 2 Overview of Voltage-Controlled Oscillators 2.1 Introduction 2.2 The Oscillators Theory 2.2.1 One-Port (Negative Resistance) View 2.2.2 Two-Port (Feedback) View 2.3 Design Concepts of Voltage-Controlled Oscillator 2.3.1 Parameters of a Voltage-Controlled Oscillator 2.3.2 Phase Noise 2.3.3 Quality Factor 2.4 Type of the LC Oscillator 2.4.1 Single Transistor Oscillator 2.4.2 One-Port Oscillator (Negative-Gm Oscillator) 2.4.3 Cross-Coupled Oscillator 2.4.4 Complementary Cross-Coupled Topology 2.5 Classification of Oscillators 2.5.1 Ring Oscillator 2.5.2 LC-Tank Oscillator 2.6 Research in RLC-Tank 2.6.1 Resistors 2.6.2 Inductor 2.6.3 Transformer 2.6.4 Capacitor 2.6.5 Varactors Chapter 3 Overview of Injection Locking Frequency Divider 3.1 Introduction 3.2 Principle of Injection Locked Frequency Divider 3.3 Locking Range Chapter 4 Varactor-less Triple-Resonance Divide-by-3 Injection-Locked Frequency Divider at High Injection Power 4.1 Introduction 4.2 Circuit Design 4.3 Measurement and Discussion Chapter 5 Capacitive Cross-Coupled Divide-by-3 Injection-Locked Frequency Divider 5.1 Introduction 5.2 Circuit Design 5.3 Measurement and Discussion Chapter 6 Divide-by-5 Injection-Locked Frequency Divider Using Triple-Injection Techniques 6.1 Introduction 6.2 Circuit Design 6.3 Measurement and Discussion Chapter 7 Wide-Locking Range LC Divide-by-6 Injection-Locked Frequency Divider 7.1 Introduction 7.2 Circuit Design 7.3 Measurement and Discussion Chapter 8 Conclusions References

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