本篇論文提出一個三階的SMASH-21三角積分調變器,此調變器解析度可以到達12.48個位元,我們將第一階的電容值加大來壓抑輸入的thermal noise,此電路採台積電0.18um CMOS製成.操作電壓在1福特,取樣頻率在2 MHz,頻寬設計在10 kHz,此架構是應用在生醫領域.

　This thesis presents a low-power modified sturdy MASH-21 delta-sigma AD converter with 12.48-bit resolution. We modified the previous architecture to three stages and enlarged the first stage capacitance to suppress thermal noise. This chip was fabricated in TSMC 0.18um CMOS process. The operating voltage is set at 1 volt. The sampling frequency is set at 2 MHz and the system bandwidth is set to 10 kHz for bio signal detection applications.

 [1] Chauchin Su; Po-Chen Lin; Hungwen LU ,” An Inverter Based 2-MHz 42μW ΔΣ ADC with 20-KHz Bandwidth and 66dB Dynamic Range” , IEEE Asian Solid-State Circuits Conference, 2006. May 2006, pp. 63-66.
 [2] Youngcheol Chae; Gunhee Han,” Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-Sigma Modulator”, IEEE J.Solid-State Circuits,vol. 44, no. 2, Nov.2009, pp. 458-472.
 [3] Szu-Chieh Liu and Kea-Tiong Tang, “A Low-Voltage Low Power Sigma Delta modulator for Bio-Potential Signals”, IEEE Life Science Systems and Applications, April. 2011, pp. 24-27.
 [4] de la Rosa, J.M.,Escalera, S., Perez-Verdu, B., Medeiro, F., Guerra, O., del Rio, R., Rodriguez-Vazquez, A., “ A CMOS 110-dB@40-kS/s programmable-gain chopper-stabilized third-order 2-1 cascade sigma-delta Modulator for low-power high-linearity automotive sensor ASICs” , IEEE J.solid-state Circuits,vol. 44,no.11, Nov. 2005 , pp. 2246-2264.
 [5] Maghari, N., Sunwoo Kwon and Un-Ku Moon , “74dB SNDR Multi-Loop Sturdy-MASH Delta Sigma Modulator Using 35dB Open-Loop Opamp Gain”, IEEE J.Solid-State Circuits, vol. 47 , no.3, Nov. 2012 , pp. 709-721.
 [6] Michel, F.; Steyaert, M.S.J. ,”A 250 mV 7.5 μW 61 dB SNDR SC ΔΣ Modulator Using Near-Threshold-Voltage-Biased Inverter Amplifiers in 130 nm CMOS”, IEEE J.Solid-State Circuits,vol. 47, no.3, Nov. 2012, pp. 709-721.
 [7] 黃濬杰 ，「低功耗之二階強健式多級三角積分類比數位轉換器｣ ，國立台灣科技大學電機工程學系碩士論文，中華名國一百零二年一月。
 [8] Szu-Chieh Liu, and Kea-Tiong Tang, “A Low voltage low-power sigma-delta modulator for bio-potential signals,” IEEE Life Science Systems and Applications Workshop, Nov. 2011, pp. 24-27.
 [9] B. Razavi, Design of Analog CMOS Integrated Circuit. US, McGraw-Hill,2001.
 [10] S. Rabii and B. A. Wooley, The Design of Low-Voltage, Low-Power Sigma-Delta Modulators. Norwood, MA: Kluwer, 1999.
 [11] P.Malcovati, S. Brigati, F. Francesconi, F.Maloberti and A. Baschirotto,”Behavioral modeling of switched-capacitor sigma-delta modulators”, IEEE Trans.Circuits Syst. I, Fund. Theory Appl., vol. 50, Mar. 2003, pp.352 -364.