本論文以返馳式功因修正電路，提出兩種抑制低頻輸出電壓漣波的改良型電路架構。其一為輸出電壓疊接的方式，使用Inverse-Buck轉換器，使其產生反向的漣波電壓進而達到漣波抑制的效果，另一種為輸出並接Buck-Boost雙向轉換器，吸收多餘的能量與提供不足的能量，降低輸出電壓漣波降到限定的範圍內。
　　由於漣波被抑制，可以使用較小的輸出電容來取代。因此，電解電容可以更換為固態電容以延長驅動器壽命。本文將詳細分析兩種改良型架構及工作模式，做為電路設計依據。製作一輸出36V/60W之雛型電路，透過電腦模擬與實際電路量測，驗證理論分析的結果。

This thesis studied two circuit topologies to reduce low-frequency output ripple voltage based on flyback power factor corrector (PFC). In the first topology, a reverse ripple voltage is produced by an Inverse-Buck convertor cascode at the output side to cancel the ripple. In the other topology, a bidirectional buck-boost converter is parallel-connected at the output to absorb/ supply power and thus reduce the ripple.
Due to ripple reduction, small output capacitance can be used. Therefore, electrolytic capacitor is replaced by solid-state capacitor in the prototype converter to prolong the lifetime. In this thesis, the operating principles and design considerations for the two circuit topologies are analyzed and discussed. 36 V/ 60 W laboratory prototypes are built and tested to verify the theoretical analysis.

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